高速折叠插值ADC采样时间失配误差校准电路设计

发布时间：2019-05-24 18:10

【摘要】：折叠插值ADC (Analog-to-Digital Converter,模数转换器)相比于全并行结构ADC在获得高速度的同时也减小了芯片的面积和功耗,在高速ADC中得到了广泛的应用。但现如今单片ADC很难达到很高采样速率的要求,因此时间交织结构ADC越来越多的被采用,然而各子ADC之间存在各种误差,会对ADC的性能造成很大影响,其中各通道间的采样时序误差是最关键也最难校准的一个环节,成为该领域研究的热点。本文对时间交织ADC通道间失配误差校准技术的研究现状做了详细的调研,针对8位,单通道采样频率500MHz的四通道折叠插值时间交织ADC,分析了各子通道间误差对ADC输出结果的影响,并通过理论分析以及行为级建模论证了设计采样时间失配误差校准电路的必要性,得出本文所述时间交织ADC各通道间的采样时序偏差应小于2.5ps。研究典型的采样时间失配误差校准技术,在此基础上确定了采用全差分模拟校准环路,将采样时序偏差转化为占空比信息进行校准的校准电路,包括整形电路、边沿检测电路、全差分连续时间积分器、跨导放大器等。其中边沿检测电路将采样时序偏差转化为占空比信息,且在电路中引入了手动调整模块,通过改变电路中流过的电流大小细微的调整检测到的占空比信息,能够进行后台调整;积分器电路中根据增益、摆幅等确定积分器中运放架构的选择和设计,积分器RC常数的确定等;跨导放大器中通过负反馈提高电路的线性度,得到了非常线性的跨导增益。最后对整个校准环路的校准效果进行了仿真验证。本文基于TSMC 0.18μmCMOS工艺,在2V电源电压下,利用Cadence Spectre软件对设计的校准电路进行仿真,仿真结果表明,对于1GHz的差分输入时钟信号,四通道采样时钟为其不同相位的二分频信号,当延迟其中一路100ps时,校准环路能自动将输出信号的采样时间间隔校准至500.308ps,当进一步改变手动控制字时,采样时间间隔被校准至499.992ps,满足了 8位四通道时间交织ADC对采样时序误差的要求。
[Abstract]:Compared with the full parallel architecture ADC, folding interpolation ADC (Analog-to-Digital Converter, Analog-to-Digital Converter) not only obtains high speed, but also reduces the area and power consumption of the chip, and has been widely used in high-speed ADC. However, nowadays, single-chip ADC is difficult to meet the requirements of high sampling rate, so the time interleaving structure ADC is more and more adopted. However, there are all kinds of errors between the sub-ADC, which will have a great impact on the performance of ADC. Among them, the sampling timing error between channels is the most critical and difficult to calibrate, which has become the focus of research in this field. In this paper, the research status of mismatch error calibration technology between time interleaving ADC channels is investigated in detail. For 8 bits, single channel sampling frequency 500MHz, four channel folding interpolation time interleaving ADC, The influence of errors between subchannels on the output results of ADC is analyzed, and the necessity of designing sampling time mismatch error calibration circuit is demonstrated by theoretical analysis and behavior level modeling. It is concluded that the sampling time series deviation between the channels of the time interleaving ADC described in this paper should be less than 2.5 PS. The typical calibration technology of sampling time mismatch error is studied. on this basis, the calibration circuit which uses full difference analog calibration loop to convert the sampling timing deviation into duty cycle information is determined, including shaping circuit and edge detection circuit. Full difference continuous time Integrator, transconductive amplifier, etc. The edge detection circuit converts the sampling timing deviation into duty cycle information, and introduces a manual adjustment module into the circuit. By changing the current size of the circuit, the detected duty cycle information can be adjusted in the background. In the Integrator circuit, the selection and design of the operational amplifier architecture and the determination of the RC constant of the Integrator are determined according to the gain and swing, and the very linear transconductivity gain is obtained by improving the linearity of the circuit by negative feedback in the transconductive amplifier. Finally, the calibration effect of the whole calibration loop is verified by simulation. In this paper, based on TSMC 0.18 渭 m CMOS process, the calibration circuit is simulated by Cadence Spectre software at 2V power supply voltage. The simulation results show that for the differential input clock signal of 1GHz, The four-channel sampling clock is its binary signal of different phases. when one of the 100ps is delayed, the calibration loop can automatically calibrate the sampling time interval of the output signal to 500.308ps. when the manual control word is further changed, the calibration loop can automatically calibrate the sampling time interval of the output signal to 500.308ps. when the manual control word is further changed, The sampling time interval is calibrated to 499.992ps, which meets the requirements of 8-bit four-channel time interleaving ADC for sampling timing error.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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