高速高精度流水线ADC设计与研究
发布时间：2019-05-26 21:33
【摘要】：模数转换器广泛应用在无线通信中,就当前的发展趋势来看,社会对于高性能的ADC提出了更大的需求,高速高精度的应用变得越来越普遍以及重要。更有甚者希望设计一种RF ADC取代传统的前端接收网络,直接采样射频信号,这从目前的发展来看并不是神话。工艺的进步固然是件好事,数字处理芯片可以以更快更低的功耗完成计算存储等任务,可是高性能模拟电路的设计却遇到了很大挑战,加上模拟电路的性能需要以功耗面积为代价,应用环境受到限制。目前的ADC依靠强大的数字校准来辅助完成转换任务,是大势所趋。本篇文章通过理论分析和仿真验证,针对流水线ADC前两级电路的设计优化,实现16bit、100M的高速高精度流水线ADC,并尝试在无采样保持结构情况下实现双通道时间交叠流水线模数转换器的可行性。主要从以下四个方面讨论分析:(1)系统结构方面。采用一种低功耗的SHA-less结构,与传统采样保持结构相比,节省了功耗的同时又贡献较少的噪声,并分析提出办法解决新架构会出现的问题。针对噪声和功耗,首先分析误差主要来源,以模块为单位逐个分析并根据性能指标推算基础模块所需实现的性能,最后提出一种噪声功耗的分析方法。(2)模拟电路方面。设计了高性能的bootstrapped采样开关、运算放大器和动态比较器,并创新提出了一种低抖动的时钟驱动器,该模块可以调整输入时钟的占空比至50%。运放结构的选择中通过各自优缺点的分析后决定使用两级米勒补偿结构,并采用了gain-boosting增益提升技术。比较器方面进行微小改进使之能有更快的响应速度。低抖动的时钟驱动器为了满足高速的应用场合,优化clock jitter,同时在后面添加纯数字的占空比稳定电路,具有极低的建立时间,用来提升时间裕度,保证ADC有更好性能和可靠性。(3)数字校准方面。利用Matlab建模仿真,通过分析并建立误差模型实现典型的dithering技术对于流水线ADC第一级的增益误差和电容不匹配的校准。(4)尝试采用双通道的时间交叠技术进行提速,对于无采样保持情况下的双通道情况进行误差分析。通过建模仿真验证其可行性。最终的电路仿真显示单通道流水线ADC可以完成100M的采样率、16比特的转换工作,并且结果良好,低频输入时SNDR为76.8d B,SFDR为100d B;高频输入时SNDR为75.7d B,SFDR为97d B。双通道实现16比特200M的性能,低频信号输入时SNDR为76.7d B,SFDR为100d B;高频输入时SNDR为75.5d B,SFDR为88d B。
[Abstract]:Analog-to-digital converter (ADC) is widely used in wireless communication. According to the current development trend, the society has put forward greater demand for high-performance ADC, and the application of high-speed and high-precision has become more and more common and important. What's more, it is not a myth to design a RF ADC to replace the traditional front-end receiving network and directly sample RF signals. Of course, the progress of the process is a good thing. The digital processing chip can complete the tasks of computing and storage with faster and lower power consumption, but the design of high performance analog circuit has encountered great challenges. In addition, the performance of analog circuits needs to be at the expense of power consumption area, and the application environment is limited. At present, ADC relies on powerful digital calibration to assist in the completion of conversion tasks, which is the general trend. In this paper, through theoretical analysis and simulation verification, the design optimization of the first two stages of pipelined ADC is carried out, and the high speed and high precision pipelined ADC, of 16bit100m is realized. The feasibility of realizing dual-channel time overlapping pipelined analog-to-digital converter without sampling and holding structure is tried. Mainly from the following four aspects of discussion and analysis: (1) the system structure. Compared with the traditional sampling and holding structure, a low power consumption SHA-less structure is adopted, which saves power consumption and contributes less noise, and analyzes and proposes a method to solve the problems of the new architecture. For noise and power consumption, the main sources of error are analyzed, and the performance of the basic module is analyzed one by one according to the performance index. Finally, an analysis method of noise power consumption is proposed. (2) Analog circuit. A high performance bootstrapped sampling switch, operational amplifier and dynamic comparator are designed, and a low jitter clock driver is proposed, which can adjust the duty cycle of the input clock to 50%. Through the analysis of their advantages and disadvantages, the two-stage Hans Muller compensation structure is decided to be used in the selection of operational amplifier structure, and the gain-boosting gain lifting technology is adopted. Minor improvements have been made in the comparator to enable it to respond faster. In order to meet the needs of high speed applications, the low jitter clock driver optimizes the clock jitter, and adds a pure digital duty cycle stable circuit to the rear, which has a very low setup time and is used to improve the time margin. Ensure better performance and reliability of ADC. (3) Digital calibration. By using Matlab modeling and simulation, the typical dithering technology is analyzed and established to calibrate the gain error and capacitance mismatch in the first stage of pipeline ADC. (4) the dual-channel time overlap technique is used to speed up the calibration of the gain error and capacitance mismatch in the first stage of pipeline ADC. The error analysis of the two-channel case without sampling and holding is carried out. Its feasibility is verified by building and imitating. The final circuit simulation shows that the single-channel pipelined ADC can complete 100m sampling rate and 16-bit conversion, and the results are good. SNDR is 76.8dB and SFDR is 100dB at low frequency input, and SNDR is 75.7 d B at high frequency input and 97dB at high frequency input. The performance of 16-bit 200m is achieved in two channels. SNDR is 76.7d B and SFDR is 100dB in low frequency signal input, SNDR is 75.5 d B in high frequency input and 88dB in high frequency input.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
本文编号：2485651
[Abstract]:Analog-to-digital converter (ADC) is widely used in wireless communication. According to the current development trend, the society has put forward greater demand for high-performance ADC, and the application of high-speed and high-precision has become more and more common and important. What's more, it is not a myth to design a RF ADC to replace the traditional front-end receiving network and directly sample RF signals. Of course, the progress of the process is a good thing. The digital processing chip can complete the tasks of computing and storage with faster and lower power consumption, but the design of high performance analog circuit has encountered great challenges. In addition, the performance of analog circuits needs to be at the expense of power consumption area, and the application environment is limited. At present, ADC relies on powerful digital calibration to assist in the completion of conversion tasks, which is the general trend. In this paper, through theoretical analysis and simulation verification, the design optimization of the first two stages of pipelined ADC is carried out, and the high speed and high precision pipelined ADC, of 16bit100m is realized. The feasibility of realizing dual-channel time overlapping pipelined analog-to-digital converter without sampling and holding structure is tried. Mainly from the following four aspects of discussion and analysis: (1) the system structure. Compared with the traditional sampling and holding structure, a low power consumption SHA-less structure is adopted, which saves power consumption and contributes less noise, and analyzes and proposes a method to solve the problems of the new architecture. For noise and power consumption, the main sources of error are analyzed, and the performance of the basic module is analyzed one by one according to the performance index. Finally, an analysis method of noise power consumption is proposed. (2) Analog circuit. A high performance bootstrapped sampling switch, operational amplifier and dynamic comparator are designed, and a low jitter clock driver is proposed, which can adjust the duty cycle of the input clock to 50%. Through the analysis of their advantages and disadvantages, the two-stage Hans Muller compensation structure is decided to be used in the selection of operational amplifier structure, and the gain-boosting gain lifting technology is adopted. Minor improvements have been made in the comparator to enable it to respond faster. In order to meet the needs of high speed applications, the low jitter clock driver optimizes the clock jitter, and adds a pure digital duty cycle stable circuit to the rear, which has a very low setup time and is used to improve the time margin. Ensure better performance and reliability of ADC. (3) Digital calibration. By using Matlab modeling and simulation, the typical dithering technology is analyzed and established to calibrate the gain error and capacitance mismatch in the first stage of pipeline ADC. (4) the dual-channel time overlap technique is used to speed up the calibration of the gain error and capacitance mismatch in the first stage of pipeline ADC. The error analysis of the two-channel case without sampling and holding is carried out. Its feasibility is verified by building and imitating. The final circuit simulation shows that the single-channel pipelined ADC can complete 100m sampling rate and 16-bit conversion, and the results are good. SNDR is 76.8dB and SFDR is 100dB at low frequency input, and SNDR is 75.7 d B at high frequency input and 97dB at high frequency input. The performance of 16-bit 200m is achieved in two channels. SNDR is 76.7d B and SFDR is 100dB in low frequency signal input, SNDR is 75.5 d B in high frequency input and 88dB in high frequency input.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
【参考文献】
相关硕士学位论文 前1条
1 汪月花;基于功耗和线性度优化的Pipeline ADC系统建模[D];电子科技大学;2008年
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