一种三段式高精度宽量程时间数字转换电路设计
发布时间：2019-06-06 18:40
【摘要】：时间数字转换(Time-to-Digital Converter, TDC)电路用于时间测量,将两个异步信号所定义的持续时间间隔转化为数字量输出。TDC电路常用于实现一定动态范围内的精密时间测量,在光子或粒子飞行时间检测、脉冲信号持续时间检测等各类系统中获得了广泛应用,有力支撑了红外传感检测、温度检测技术的发展。单模式TDC电路只有一种时间量化基本单位,无法兼顾高精度与宽量程的共同需求。因此,为了突破测量精度提高与量程范围扩展的相互制约关系,TDC必须依靠大小不同的量化单位TDC之间的配合,构成多段式TDC,有效提高时间检测的动态范围,提升检测精度。本文提出的三段式TDC是在经典两段式TDC基础上改进得到：高段LFSR计数式TDC保持不变,实现所需的宽量程检测;同时将延迟式TDC的控制电压改进为DLL控制提供,提高中段TDC的性能水平,并在此基础上进一步引入游标细分辨TDC,突破数字门电路最小延迟下限,实现高精度量化。与其他三段式TDC结构相比,本设计在精度上突破门延迟限制基础上,高段位实现了宽动态范围的量程扩展,实现了兼顾精度和宽量程的共同需求。除此以外,本设计基于Dual-DLL架构,产生的压控电压稳定性明显优于开环补充结构,在抑制环振频率的相位噪声或时钟抖动方面具有明显优势。本论文设计的高精度与宽量程三段式TDC电路,在维持原有量程不变的条件下,其时间检测分辨率突破了工艺决定的门延迟时间限制。本设计采用TSMC 0.35μm标准工艺,通过Cadence EDA工具验证,完成了整个电路前仿、版图与后仿及流片验证。测试结果显示,在40MHz输入时钟条件下,15bit三段式TDC测试量程可达4gs,同时转换精度可限制在0.25ns以内,温度-40℃～100℃时功能正常,满足设计要求。
[Abstract]:Time digital conversion (Time-to-Digital Converter, TDC) circuit is used for time measurement, converting the duration interval defined by two asynchronous signals into digital output. TDC circuits are often used to realize precise time measurement in a certain dynamic range. It has been widely used in photonic or particle flight time detection, pulse signal duration detection and other systems, which strongly supports the development of infrared sensing detection and temperature detection technology. Single mode TDC circuits have only one basic unit of time quantification, which can not take into account the common needs of high precision and wide range. Therefore, in order to break through the mutual restriction between the improvement of measurement accuracy and the expansion of range, TDC must rely on the cooperation between quantitative units of different sizes to form a multi-segment TDC, to effectively improve the dynamic range of time detection and improve the detection accuracy. The three-stage TDC proposed in this paper is improved on the basis of the classical two-stage TDC: the high-segment LFSR counting TDC remains unchanged and the required wide range detection is realized; At the same time, the control voltage of delayed TDC is improved for DLL control, and the performance level of middle TDC is improved. on this basis, Vernier fine resolution TDC, is further introduced to break through the minimum delay lower limit of digital gate circuit to realize high precision quantification. Compared with other three-stage TDC structures, on the basis of breaking through the limitation of gate delay in precision, the high segment bit realizes the range expansion of wide dynamic range and realizes the common demand of taking into account the accuracy and wide range. In addition, based on Dual-DLL architecture, the voltage-controlled voltage stability of this design is obviously better than that of open-loop supplementary structure, and it has obvious advantages in suppressing the phase noise or clock jitter of ring vibration frequency. In this paper, the high precision and wide range three-stage TDC circuit is designed, and its time detection resolution breaks through the gate delay time limit determined by the process under the condition that the original range is unchanged. The design adopts TSMC 0.35 渭 m standard process and is verified by Cadence EDA tool. The whole circuit is verified by front imitation, layout, rear imitation and flow chip verification. The test results show that under the condition of 40MHz input clock, the test range of 15bit three-stage TDC can reach 4 GS, and the conversion accuracy can be limited to 0.25ns. The function is normal at-40 鈩，
本文编号：2494514
[Abstract]:Time digital conversion (Time-to-Digital Converter, TDC) circuit is used for time measurement, converting the duration interval defined by two asynchronous signals into digital output. TDC circuits are often used to realize precise time measurement in a certain dynamic range. It has been widely used in photonic or particle flight time detection, pulse signal duration detection and other systems, which strongly supports the development of infrared sensing detection and temperature detection technology. Single mode TDC circuits have only one basic unit of time quantification, which can not take into account the common needs of high precision and wide range. Therefore, in order to break through the mutual restriction between the improvement of measurement accuracy and the expansion of range, TDC must rely on the cooperation between quantitative units of different sizes to form a multi-segment TDC, to effectively improve the dynamic range of time detection and improve the detection accuracy. The three-stage TDC proposed in this paper is improved on the basis of the classical two-stage TDC: the high-segment LFSR counting TDC remains unchanged and the required wide range detection is realized; At the same time, the control voltage of delayed TDC is improved for DLL control, and the performance level of middle TDC is improved. on this basis, Vernier fine resolution TDC, is further introduced to break through the minimum delay lower limit of digital gate circuit to realize high precision quantification. Compared with other three-stage TDC structures, on the basis of breaking through the limitation of gate delay in precision, the high segment bit realizes the range expansion of wide dynamic range and realizes the common demand of taking into account the accuracy and wide range. In addition, based on Dual-DLL architecture, the voltage-controlled voltage stability of this design is obviously better than that of open-loop supplementary structure, and it has obvious advantages in suppressing the phase noise or clock jitter of ring vibration frequency. In this paper, the high precision and wide range three-stage TDC circuit is designed, and its time detection resolution breaks through the gate delay time limit determined by the process under the condition that the original range is unchanged. The design adopts TSMC 0.35 渭 m standard process and is verified by Cadence EDA tool. The whole circuit is verified by front imitation, layout, rear imitation and flow chip verification. The test results show that under the condition of 40MHz input clock, the test range of 15bit three-stage TDC can reach 4 GS, and the conversion accuracy can be limited to 0.25ns. The function is normal at-40 鈩，
本文编号：2494514
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