基于△∑调制技术的小数分频器设计
发布时间：2019-06-07 08:55
【摘要】：小数型频率合成器具有快速锁定、高频率分辨率以及低相位噪声等方面的优势,在无线射频通信芯片中得到了广泛的应用。小数分频器作为环路中的核心模块之一,完成可编程且连续变化的分频功能,是实现高性能小数型频率合成器的前提和关键。论文的主要工作是设计一款基于△∑调制技术的小数分频器。论文首先综述了小数分频技术的发展和研究现状,从系统上分析了小数分频的基本原理,总结了△∑调制器的性能优化技术。为了评估系统环路中小数分频器对总输出相位噪声的贡献,建立了小数分频器的噪声模型。针对△∑调制器的设计,采用Simulink工具对△∑调制器进行建模分析,确定了△∑调制器的基本结构和阶数,提出一种HK-MASH结构和嵌套的混合基调制器相结合的设计方案,改善了输出频谱性能的同时消除了有限字长效应引入的频率误差。针对多模可编程分频器的设计,采用SCL结构与TSPC结构相结合的方式实现分频器功耗的降低,最后根据指标要求采用分频比扩展技术设计了一款具有0.5分频步长,分频比的范围达到32-127.5的多模可编程分频器。论文基于SMIC 0.18μmCMOS工艺,完成了小数分频器的原理图及版图设计,并进行了仿真验证。后仿真结果表明频率合成器的锁定时间小于10μs,其中小数分频器的工作频率范围达到1.5GHz-2.8GHz,频率分辨率为25Hz,全频段内相位噪声优于-135dBc/Hz@10KHz,1.8V的电源电压下消耗的电流小于2.4mA,达到了设计要求。
[Abstract]:Decimal frequency synthesizer has been widely used in radio frequency communication chips because of its advantages of fast locking, high frequency resolution and low phase noise. As one of the core modules in the loop, the decimal frequency divider completes the programmable and continuous frequency division function, which is the premise and key to realize the high performance decimal frequency synthesizer. The main work of this paper is to design a decimal frequency divider based on Sigma modulation technology. In this paper, the development and research status of decimal frequency division technology are reviewed, the basic principle of decimal frequency division is analyzed systematically, and the performance optimization technology of Sigma modulator is summarized. In order to evaluate the contribution of the system loop decimal divider to the total output phase noise, the noise model of the decimal divider is established. Aiming at the design of Sigma modulator, the Simulink tool is used to model and analyze the Sigma modulator, the basic structure and order of Sigma modulator are determined, and a design scheme combining HK-MASH structure with nesting hybrid tuner is proposed. The output spectrum performance is improved and the frequency error introduced by the finite word length effect is eliminated. Aiming at the design of multimode programmable frequency divider, the power consumption of frequency divider is reduced by combining SCL structure with TSPC structure. Finally, a frequency division step length is designed by using frequency division ratio expansion technology according to the requirements of the index. A multimode programmable frequency divider with a frequency division ratio of 32 鈮，
本文编号：2494674
[Abstract]:Decimal frequency synthesizer has been widely used in radio frequency communication chips because of its advantages of fast locking, high frequency resolution and low phase noise. As one of the core modules in the loop, the decimal frequency divider completes the programmable and continuous frequency division function, which is the premise and key to realize the high performance decimal frequency synthesizer. The main work of this paper is to design a decimal frequency divider based on Sigma modulation technology. In this paper, the development and research status of decimal frequency division technology are reviewed, the basic principle of decimal frequency division is analyzed systematically, and the performance optimization technology of Sigma modulator is summarized. In order to evaluate the contribution of the system loop decimal divider to the total output phase noise, the noise model of the decimal divider is established. Aiming at the design of Sigma modulator, the Simulink tool is used to model and analyze the Sigma modulator, the basic structure and order of Sigma modulator are determined, and a design scheme combining HK-MASH structure with nesting hybrid tuner is proposed. The output spectrum performance is improved and the frequency error introduced by the finite word length effect is eliminated. Aiming at the design of multimode programmable frequency divider, the power consumption of frequency divider is reduced by combining SCL structure with TSPC structure. Finally, a frequency division step length is designed by using frequency division ratio expansion technology according to the requirements of the index. A multimode programmable frequency divider with a frequency division ratio of 32 鈮，
本文编号：2494674
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