SerDes接收端关键技术的研究与设计

发布时间：2019-06-10 09:01

【摘要】：随着网络技术和硬件制造技术的迅猛发展,系统间的数据传输量快速增加,导致传输接口的数据传输速率成为了阻碍系统性能提升的关键因素。并行传输技术抗干扰能力弱,易产生串扰、时钟偏斜等现象,导致其数据传输速率难以提升。而串行传输技术可以有效解决这些问题使传输速率达到更高水平,再加上端口少、功耗低等优点,串行链接技术(SerDes)受到越来越多的关注,逐渐成为数据传输的主流技术。本文通过对SerDes系统的研究,基于SMIC 0.13μm的CMOS工艺对SerDes接收端的信号丢失检测电路和时钟数据恢复电路进行了研究设计,并提出了一种抖动容限的仿真验证方法。信号丢失检测电路通过检测输入信号的差分摆幅值来滤除严重失真的信号和耦合到输入端的噪声。本文设计的信号丢失检测电路的阈值电压可以跟随输入信号的共模电平变化,使检测结果不受输入信号共模电平的影响。时钟数据恢复电路采用相位插值的结构设计,本文主要给出了相位跟踪环路的电路设计,包括采样电路、相位检测电路、表决器、插值控制电路和相位插值电路。其中,相位检测电路采用Bang-Bang型的半速率相位检测器,采样时钟频率不超过数据传输速率,提高了数据传输速率。相位插值的方法是先将全周期分为8个相位区间,然后在时钟所在的相位区间内对时钟相位进行调节。该方法减小了插值步长,有利于准确调节时钟相位。本文还提出了一种抖动容限的仿真验证方法,通过VerilogA语言产生带抖动的伪随机数据作为测试信号,通过Python脚本判断仿真输出信号是否出错。该方法在芯片设计阶段对抖动容限进行仿真验证,有效的降低了流片风险。抖动容限仿真结果表明,当抖动频率在0.1MHz到10MHz之间时,抖动容限为0.61UI。在SerDes电路设计完成后,完成该芯片的版图设计并将该芯片流片,然后对流片后的SerDse芯片进行测试。SerDes芯片的版图面积为2363×2422μm。测试结果表明该芯片工作正确,数据传输速率可达到2.5Gbps。
[Abstract]:With the rapid development of the network technology and hardware manufacturing technology, the data transmission rate among the systems is rapidly increased, resulting in the data transmission rate of the transmission interface becoming the key factor to hinder the performance of the system. The anti-interference ability of parallel transmission technology is weak, it is easy to generate cross-talk, clock skew, and so on, which causes the data transmission rate to be difficult to increase. The serial transmission technology can effectively solve these problems, so that the transmission rate can reach a higher level, and the serial link technology (SerDes) is more and more concerned and gradually becomes the mainstream technology of data transmission. Based on the research of SerDes system, the signal loss detection circuit and clock data recovery circuit of SerDes receiving end are designed based on the CMOS process of the SMIC 0.13. m u.m, and a method of simulation and verification of the jitter tolerance is proposed. The signal loss detection circuit filters out the signal of the severe distortion and the noise coupled to the input terminal by detecting the differential swing amplitude of the input signal. The threshold voltage of the signal loss detection circuit designed in this paper can follow the common-mode level change of the input signal, so that the detection result is not affected by the common-mode level of the input signal. The clock data recovery circuit adopts the structure design of phase interpolation, and the circuit design of the phase tracking loop is mainly given in this paper, including the sampling circuit, the phase detection circuit, the voter, the interpolation control circuit and the phase interpolation circuit. The phase detection circuit adopts the half-rate phase detector of the Bang-Bang type, the sampling clock frequency does not exceed the data transmission rate, and the data transmission rate is improved. The phase interpolation method comprises the following steps of: firstly, dividing the full period into 8 phase sections, and then adjusting the clock phase in the phase section where the clock is located. The method reduces the interpolation step size and is beneficial to the accurate adjustment of the clock phase. In this paper, a simulation and verification method for jitter tolerance is presented, and the pseudo-random data with jitter is generated as a test signal through Verilog language, and the error of the simulation output signal is judged by the Python script. In that method, the jitter tolerance is simulated and verified at the design stage of the chip, and the risk of the flow sheet is effectively reduced. The jitter tolerance simulation results show that the jitter margin is 0.61 UI when the jitter frequency is between 0.1 MHz and 10 MHz. After the SerDes circuit design is completed, the layout of the chip is completed and the chip flow is completed, and then the SerDes chip after the convection chip is tested. The serial area of the SerDes chip is 2363-2422. m u.m. The test results show that the chip is working correctly and the data transmission rate can reach 2.5 Gbps.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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