基于FPGA的RC5加密芯片的设计与实现

发布时间：2019-06-18 19:40

【摘要】：伴随着我国国民经济的快速发展和社会信息化进程的加快,信息的安全问题也随之得到了越来越多的关注,对信息安全的核心密码技术的研究就变得重要而紧迫。本文介绍了基于FPGA的RC5加密芯片的设计与实现,RC5的字长、加密轮数密钥长度都可以改变,而且只涉及初等运算,这使它具有很好的适应性和很高的运算速度,非常适用于硬件和软件实现,从而具有广泛的应用。本文在分析RC5加密算法原理的基础上提出了一种基于全循环模式的规模优化的电路设计方案,即在芯片中只设置实现一轮加／解密变换所需要的硬件电路,在有限状态机的控制下,通过循环使用该电路12次完成对一组数据的12轮加／解密变换。基于上述设计思想,本文针对字长为32位、加密轮数为12轮、密钥长度为16个字节的RC5加密芯片的体系结构进行了详细设计,建立了该芯片的Verilog HDL模型并进行了功能仿真,基于FPGA对该Verilog HDL模型进行了综合优化、布局布线、静态时序分析,最终基于FPGA实现了RC5-32/12/16加密芯片,并在真实的应用环境中对其进行了测试。测试结果表明所设计的RC5-32/12/16加密芯片实现了预期的功能。本论文研究中使用的EDA工具软件是Modelsim10.0和QuartusⅡ 9.1,硬件实现使用的FPGA芯片是ALTERA公司的Cyclone EP1C12Q240C8.实验结果表明,RC5加密芯片共使用了1782个逻辑单元,系统的时钟频率可以达到64.4MHz,信息加／解密的峰值速度为343Mb/s,系统功耗为82.54mW。
[Abstract]:With the rapid development of our national economy and the acceleration of the social information process, the security of information has also been paid more and more attention, and the research on the core cipher technology of information security becomes more and more important and urgent. This paper introduces the design and implementation of the RC5 encryption chip based on FPGA, the word length of the RC5 and the length of the encryption wheel number can be changed, and only the elementary operation is involved, which makes it have good adaptability and high operation speed, and is very suitable for the realization of hardware and software. So as to have a wide application. Based on the analysis of the principle of the RC5 encryption algorithm, a circuit design scheme based on the full-loop mode is proposed, that is, only the hardware circuit needed to realize the one-round addition/ decryption transform is set in the chip, and under the control of the finite state machine, The 12-wheel-plus/ decryption transformation of a set of data is completed by a loop using the circuit 12 times. Based on the above-mentioned design idea, the architecture of the RC5 encryption chip with a word length of 32 bits, an encryption wheel number of 12 wheels and a key length of 16 bytes is designed in detail, the Verilog HDL model of the chip is established and the function simulation is carried out, Based on the FPGA, the Verilog HDL model is comprehensively optimized, the layout and the static timing analysis are carried out, and the RC5-32/12/16 encryption chip is finally realized on the basis of the FPGA, and the test is carried out in the real application environment. The test results show that the designed RC5-32/12/16 encryption chip has the expected function. The EDA tool software used in this thesis is Modelsim10.0 and Quartus II.1. The FPGA chip for hardware implementation is the Cyclone EP1C12Q240C8 of ALTERA. The experimental results show that the RC5 encryption chip uses 1782 logic units, the clock frequency of the system can reach 64.4 MHz, the peak speed of the information addition/ decryption is 343Mb/ s, and the power consumption of the system is 82.54 mW.
【学位授予单位】：青岛科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402;TN918.4

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