用于3-GHz无线通信CMOS多增益低噪声放大器的设计

发布时间：2022-12-23 20:40

　　随着无线网络传感器应用领域对无线连接的要求不断增长,物联网和射频识别方面都将研究力量集中在提出低成本、低功耗和更小型化的SOC设计方案上。由于CMOS技术在低成本和高集成度方面具有其独特的优势,因此大多数收发机模块在不影响性能的条件下都采用此技术设计。因为LNA是接收机端的第一个模块,整个接收机的灵敏度和噪声都取决于LNA的性能好坏。因此,根据ZigBee、IEEE802.11xx、BLE和RFID等不同应用标准设计LNA将变得更具有挑战性。基于不同的无线应用标准,本论文主要对实现集成多重增益、低噪声、差分结构、高IIP3线性和低功耗的低噪声放大器进行研究,设计了工作于3-3.04GHz的CMOS低噪声放大器。所设计的LNA是基于CMOS GF-130nm工艺的,由输入匹配、多核心放大器、输出匹配和差分结构组成。高频情况下,LNA的灵敏度和功耗通常严格地取决于输入匹配。当它接收的信号从弱输入射频信号变化到更高的时候会消耗更多功率。针对这个问题,本文提出了一种多重共源共栅技术以实现不同的增益模式,且不影响输入输出匹配性能。为了实现较低的低噪声设计,本文提出采用高Q值中心抽头电感来实现低噪... 

【文章页数】：87 页

【学位级别】：硕士

【文章目录】：
摘要
Abstract
Chapter 1 Introduction
    1.1 Overview
    1.2 Receiver Architecture
    1.3 3-GHz Transceiver
    1.4 Previous Work
    1.5 Scope & Organization of Thesis
Chapter 2 Matching Networks
    2.1 Introduction
    2.2 Matching Networks
        2.2.1 RLC Parallel Matching Network
        2.2.2 RLC Series Matching Network
        2.2.3 Q-Factor
        2.2.4 Maximum Power Transformation
        2.2.5 L-match Topology
        2.2.6 π-match Topology
        2.2.7 T-match Topology
    2.3 Summary
Chapter 3 Two-Port Network, Bandwidth & Noise
    3.1 Introduction
    3.2 Two-Port Network
        3.2.1 Y-Parameters
        3.2.2 S-Parameters
        3.2.3 Smith Chart
    3.3 Bandwidth Estimation
    3.4 Noise
        3.4.1 Thermal Noise
        3.4.2 Shot Noise
        3.4.3 Flicker Noise
    3.5 Summary
Chapter 4 LNA Design Constraints
    4.1 Introduction
    4.2 Noise Considerations
        4.2.1 Noise Figure
        4.2.2 Noise Temperature
    4.3 Network Gain
        4.3.1 Power Gain
        4.3.2 Transducer Gain
        4.3.3 Available Gain
    4.4 Linearity
        4.4.1 1-dB Compression Point (P1dB)
        4.4.2 Third Order Intercept Point (IP3)
    4.5 Summary
Chapter 5 Schematic & Layout Design
    5.1 Introduction
    5.2 Basic Topologies
        5.2.1 LNA with Input Shunt Resistor
        5.2.2 Common Gate LNA (CG)
        5.2.3 Resistive Feedback LNA
        5.2.4 Common Source LNA with Inductive Degeneration (CS)
        5.2.5 Comparison of Different Topologies
        5.2.6 Comparison of Different Design and Optimization Principles
    5.3 Schematic Design
        5.3.1 Input Matching
        5.3.2 Multigain Cascode Structure
        5.3.3 Differential Structure
        5.3.4 Inductive Source Degeneration
        5.3.5 Output Matching
        5.3.6 Biasing Structure
        5.3.7 Full Schematic Diagram
    5.4 Layout Design
    5.5 Post Simulation Results
    5.6 Summary
Chapter 6 Conclusion & Future Work
    6.1 Conclusion
    6.2 Future Work
    6.3 Summary
References
Acknowledgement
List of Publications



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