基于FPGA的GPS接收机相关器的设计与实现

发布时间：2018-04-13 14:14

本文选题：GPS相关器 + FPGA　；参考：《北京工业大学》2013年硕士论文

【摘要】：全球导航定位系统(GPS, Global Positioning System)是实时全球卫星定位导航系统，具有定位精度高、全天候以及实时性强等诸多优点，对经济建设和国防建设都具有非常重要的战略意义，尤其是在近几年我国自然灾害频发，在应对救助救援过程中，GPS定位系统扮演着尤为重要的角色。而相关器设计是GPS接收机的核心部分,影响着GPS接收机的性能。论文主要研究内容是GPS接收机数字相关器在FPGA中的设计与实现。论文首先简单介绍了GPS全球定位系统以及国内外发展现状，接着依据GPS信号的基本构成，说明GPS系统定位原理和接收机原理；通过对比分析目前使用三种捕获方法：时域滑动相关捕获、基于FFT的频域并行搜索捕获和基于数字匹配滤波器的快速捕获，设计采用捕获速度最快的数字匹配滤波器的方案。然后对相关器整体结构进行规划设计，详细划分功能模块。设计采用折叠匹配滤波器捕获，跟踪通道内载波跟踪环路采用Costas环，消除数据码调制产生的相位翻转；码跟踪环则采用非相干解调设计。同时对各级组成模块的设计具体参数进行了详细分析。最后使用Verilog HDL语言在Xilinx ISE10.1软件平台中编写实现设计电路，进行仿真测试和验证调试。借助第三方仿真软件Modelsim SE10.0a对设计实现的GPS相关器子模块电路进行时序仿真调试，，其中包括时基发生器、重采样量化模块、折叠数字匹配滤波器模块、跟踪通道内个子模块有本地载波发生器模块、本地复现伪码发生器模块、积分清零器模块等。最终调试验证出正确的GPS相关器电路。
[Abstract]:GPS (Global Positioning system) is a real-time global positioning and navigation system, which has many advantages, such as high positioning accuracy, all-weather and real-time, etc. It has very important strategic significance for economic construction and national defense construction.Especially in recent years, natural disasters occur frequently in China, and GPS positioning system plays a very important role in the rescue and rescue process.Correlator design is the core part of GPS receiver, which affects the performance of GPS receiver.The main content of this thesis is the design and implementation of GPS receiver digital correlator in FPGA.Firstly, the paper introduces the GPS global positioning system and its development status at home and abroad, and then explains the positioning principle and receiver principle of GPS system according to the basic structure of GPS signal.By comparing and analyzing three kinds of acquisition methods: time-domain sliding correlation acquisition, frequency-domain parallel search acquisition based on FFT and fast acquisition based on digital matched filter, the scheme of adopting the fastest digital matched filter is designed.Then, the overall structure of the correlator is planned and designed, and the functional modules are divided in detail.The design uses folding matched filter to capture the carrier tracking loop in the tracking channel and Costas loop to eliminate the phase flip generated by the modulation of the data code while the code tracking loop is designed by non-coherent demodulation.At the same time, the design parameters of each component module are analyzed in detail.Finally, Verilog HDL language is used to write the design circuit in the Xilinx ISE10.1 software platform, and the simulation test and debugging are carried out.With the help of the third party simulation software Modelsim SE10.0a, the timing simulation debugging of the GPS correlator sub-module is carried out, including time base generator, resampling quantization module, folding digital matched filter module, etc.There are local carrier generator module, local reappearance pseudo code generator module and integral zero cleaner module in the tracking channel.Finally, the correct GPS correlator circuit is verified by debugging.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：P228.4

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