GPS捕获系统的FPGA实现及其验证技术研究

发布时间：2018-06-06 17:22

本文选题：GPS信号捕获 + 功能验证　；参考：《西安电子科技大学》2013年硕士论文

【摘要】：随着GPS产品需求的增加，以及集成电路设计技术的快速发展，越来越多的公司投身于GPS产品的开发。构建一个通用的GPS信号处理系统及其验证平台，将减少产品设计和产品验证的时间，大大降低产品的研发周期。本文重点研究了GPS捕获算法及其硬件实现技术，并在此基础上搭建了分层、可重用、多覆盖率统计的验证平台。目前，GPS信号的捕获多采用传统时域相关捕获法，这需要大量硬件资源，实时性很差。如果采用FFT并行捕获方式，将时域N点相关运算转换到频域，只需N次乘法运算，即可实现对一个载波频率下的所有C/A码相位的搜索，相比时域下的N~2次乘法运算，运算量大大减小。为满足FPGA资源要求，本文提出平均采样技术，以改进FFT并行捕获法；在不影响捕获性能的前提下，将中频数据采样成1024点，最终简化硬件实现过程。本文在模拟了5000点GPS中频采样信号后，实现FFT并行捕获法、改进后的FFT并行捕获法的Matlab仿真，并使用Verilog完成了改进方法的FPGA设计。结果显示，改进后的FFT并行捕获法，可以实现捕获功能，且具有较低的硬件资源使用率，硬件实现方式得以简化。就改进后的FPGA设计而言，其捕获部分的验证需要多达1000个测试用例；对于HDLC帧模块的验证，至少需要13个测试用例。如果手动编写，工作量巨大，，且测试用例不具有重用性，结果对比也很费精力。本文提出使用System Verilog验证语言，构建分层结构的验证平台，降低验证组件的关联性，实现组件重用；应用约束化随机激励、事物级、覆盖率统计、断言、脚本语言等验证技术，使用8个平台组件即可实现大量测试激励生成和输出信号自动比对，大大减少测试用例个数，实现测试数据收集自动化，降低工作量。采用代码覆盖率、功能覆盖率、断言覆盖率统计，对测试结果进行收集和分析，实现对捕获系统的充分验证。
[Abstract]:With the increase of the demand of GPS products and the rapid development of integrated circuit design technology , more and more companies have invested in the development of GPS products . A universal GPS signal processing system and its verification platform will reduce the time for product design and product verification and greatly reduce the R & D period of the product . This paper focuses on the GPS capture algorithm and its hardware implementation technology , and builds a verification platform of layered , reusable and multi - coverage statistics .

In order to meet the requirements of FPGA resources , the average sampling technique is proposed in this paper to improve the FFT parallel capture method .
In this paper , the IF data is sampled into 1024 points without affecting the capture performance , and finally the hardware realization process is simplified . Based on the simulation of the 5000 - point GPS IF sampling signal , the FFT parallel capture method is realized , the improved FFT parallel acquisition method is simulated , and the FPGA design of the improved method is completed by using verilog . The result shows that the improved FFT parallel acquisition method can realize the capture function , and has lower hardware resource utilization rate , and the hardware implementation mode is simplified .

As far as the improved FPGA design is concerned , the verification of the capture part of the FPGA needs up to 1000 test cases ;
For the verification of HDLC frame module , there are at least 13 test cases . If it is written manually , the workload is huge , and the test cases do not have reusability , the comparison of results is also very energy . This paper presents a verification platform using System verilog to build a hierarchical structure , which can reduce the relevance of the verification component and realize component reuse .
The test results are collected and analyzed with code coverage , function coverage and assertion coverage statistics , and sufficient verification of the acquisition system is realized .
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：P228.4

【参考文献】