真空定向凝固去除硅中挥发性杂质及其应用研究
发布时间:2018-08-02 20:14
【摘要】:多晶硅是光伏发电的基本材料,物理冶金法因其成本低、工艺简单、设备投资少等优势将逐步取代西门子法成为多晶硅材料生产的主要技术。作为冶金法工艺流程中的核心技术——真空定向凝固可以实现多晶硅的提纯与铸锭。然而,真空定向凝固一些关键技术还没有突破,导致其制备多晶硅的潜力并没有充分发挥。本文基于真空表面挥发和定向凝固分凝原理,进行了真空定向凝固去除硅中挥发性杂质的动力学研究,推导并验证了一个适合工业化真空定向凝固去除硅中挥发性杂质的数学模型。通过计算探讨了熔炼温度、固-液相边界层厚度和凝固速率对挥发性杂质有效分凝系数的影响。结果表明,熔炼温度上升或固-液边界层厚度变薄可导致硅中挥发性杂质的有效分凝系数变小,但幅度不大,且其减小趋势逐步放缓。凝固速率的降低导致杂质的有效分凝系数降低,且这种影响决定了挥发性杂质的分凝效果。结合多晶硅铸锭炉特点,本文选取了隔热板下拉速率作为多晶硅铸锭炉提纯多晶硅工艺改进的对象。通过不同高度下的杂质分布,反推出硅锭高度与有效分凝系数直接的关系。将其对应于理想状态下的有效分凝系数公式,得到了最佳有效分凝系数时凝固速率与硅锭凝固时间之间的关系。考虑到杂质去除和晶体生长两种因素,研究获得了铸锭炉提纯和铸锭提纯兼顾铸锭提纯两套工艺。本文分别采用电感耦合等离子体发射光谱仪(ICP-AES)、WT2000面扫描少子寿命测试仪、四探针测电阻法分别对两套工艺产出硅锭样品的杂质含量、少子寿命、电阻率进行检测。结果表明,提纯工艺产出硅锭中,杂质铜的含量均低于0.5ppmw,杂质磷的含量低于3ppmw,其他金属杂质均低于检测值。样品的少子寿命平均值在0.61μs到0.75μs范围内。中部样品的电阻率在0.2 Ω·cm~0.6 Ω·cm范围之内,硅锭边部样品的电阻率在0.15 Ω·cm-0.5 Ω-·cm范围之内;提纯兼顾工艺产出硅锭中,杂质铁和钛的含量均低于仪器的检测值,其余硅中金属杂质含量基本低于lppmw。少子寿命的平均值在5.851μs到6.466μs之间。中部样品的电阻率在0.25 Ω·cm-0.45Ω.cm范围之内,边部样品的电阻率在0.15 Ω·cm~0.5 Ω·cm范围之内。此外,根据杂质分布公式计算了硅锭成品的切割位置。根据计算位置切割硅锭相比原有切割位置直接提高硅锭收得率3.5~4%,单炉(500kg)提高产量15-20kg。
[Abstract]:Polycrystalline silicon is the basic material for photovoltaic power generation. Because of its advantages of low cost, simple process and less equipment investment, polycrystalline silicon process will gradually replace Siemens process as the main technology of polysilicon material production. As the core technology of metallurgical process, vacuum directional solidification can realize the purification and ingot of polysilicon. However, some key technologies of vacuum directional solidification have not been broken through, and the potential of preparing polysilicon has not been fully realized. Based on the principle of vacuum surface volatilization and directional solidification separation, the kinetics of removing volatile impurities from silicon by vacuum directional solidification has been studied in this paper. A mathematical model for the removal of volatile impurities in silicon by industrial vacuum directional solidification was derived and verified. The effects of melting temperature, solid-liquid boundary layer thickness and solidification rate on the effective segregation coefficient of volatile impurities were investigated. The results show that the increase of melting temperature or the thickness of solid-liquid boundary layer can result in the decrease of effective segregation coefficient of volatile impurities in silicon, but the decrease trend is slowing down gradually. The decrease of solidification rate leads to the decrease of effective segregation coefficient of impurity, and this effect determines the coagulating effect of volatile impurity. According to the characteristics of polycrystalline silicon ingot furnace, this paper selects the pull-down rate of heat insulation board as the object of improving the process of purification of polysilicon ingot furnace. Through the impurity distribution at different heights, the direct relationship between the silicon ingot height and the effective segregation coefficient is deduced. The relationship between the solidification rate and the solidification time of silicon ingot is obtained by using the formula of effective segregation coefficient corresponding to the ideal state. Considering the two factors of impurity removal and crystal growth, two processes of ingot purification and ingot purification were obtained. In this paper, the impurity content, minority carrier lifetime and resistivity of silicon ingot samples produced by two sets of processes were measured by inductively coupled plasma emission spectrometer (ICP-AES) and WT2000 scanning minority carrier lifetime tester and four-probe resistance method respectively. The results show that the content of impurity copper is lower than 0.5ppmw. the content of impurity phosphorus is lower than 3ppmw. the other metal impurity is lower than the detection value. The average minority carrier lifetime of the sample ranges from 0.61 渭 s to 0.75 渭 s. The resistivity of the middle sample is within the range of 0. 2 惟 cm~0.6 惟 cm, the resistivity of the sample at the edge of the silicon ingot is within 0. 15 惟 cm-0.5 惟-cm, and the content of impurity iron and titanium in the silicon ingot produced by the purification process is lower than the measured value of the instrument. The content of metal impurity in other silicon is lower than that in lppmw. The average minority carrier lifetime ranges from 5.851 渭 s to 6.466 渭 s. The resistivity of the middle sample is within the range of 0.25 惟 cm-0.45 惟 路cm, and the resistivity of the edge sample is within the range of 0.15 惟 cm~0.5 惟 cm. In addition, the cutting position of the finished silicon ingot was calculated according to the impurity distribution formula. According to the calculated position, the yield of silicon ingot is directly increased by 3.5 ~ 4% compared with the original cutting position, and the output of single furnace (500kg) is increased by 15-20 kg.
【学位授予单位】:昆明理工大学
【学位级别】:硕士
【学位授予年份】:2015
【分类号】:TQ127.2
本文编号:2160598
[Abstract]:Polycrystalline silicon is the basic material for photovoltaic power generation. Because of its advantages of low cost, simple process and less equipment investment, polycrystalline silicon process will gradually replace Siemens process as the main technology of polysilicon material production. As the core technology of metallurgical process, vacuum directional solidification can realize the purification and ingot of polysilicon. However, some key technologies of vacuum directional solidification have not been broken through, and the potential of preparing polysilicon has not been fully realized. Based on the principle of vacuum surface volatilization and directional solidification separation, the kinetics of removing volatile impurities from silicon by vacuum directional solidification has been studied in this paper. A mathematical model for the removal of volatile impurities in silicon by industrial vacuum directional solidification was derived and verified. The effects of melting temperature, solid-liquid boundary layer thickness and solidification rate on the effective segregation coefficient of volatile impurities were investigated. The results show that the increase of melting temperature or the thickness of solid-liquid boundary layer can result in the decrease of effective segregation coefficient of volatile impurities in silicon, but the decrease trend is slowing down gradually. The decrease of solidification rate leads to the decrease of effective segregation coefficient of impurity, and this effect determines the coagulating effect of volatile impurity. According to the characteristics of polycrystalline silicon ingot furnace, this paper selects the pull-down rate of heat insulation board as the object of improving the process of purification of polysilicon ingot furnace. Through the impurity distribution at different heights, the direct relationship between the silicon ingot height and the effective segregation coefficient is deduced. The relationship between the solidification rate and the solidification time of silicon ingot is obtained by using the formula of effective segregation coefficient corresponding to the ideal state. Considering the two factors of impurity removal and crystal growth, two processes of ingot purification and ingot purification were obtained. In this paper, the impurity content, minority carrier lifetime and resistivity of silicon ingot samples produced by two sets of processes were measured by inductively coupled plasma emission spectrometer (ICP-AES) and WT2000 scanning minority carrier lifetime tester and four-probe resistance method respectively. The results show that the content of impurity copper is lower than 0.5ppmw. the content of impurity phosphorus is lower than 3ppmw. the other metal impurity is lower than the detection value. The average minority carrier lifetime of the sample ranges from 0.61 渭 s to 0.75 渭 s. The resistivity of the middle sample is within the range of 0. 2 惟 cm~0.6 惟 cm, the resistivity of the sample at the edge of the silicon ingot is within 0. 15 惟 cm-0.5 惟-cm, and the content of impurity iron and titanium in the silicon ingot produced by the purification process is lower than the measured value of the instrument. The content of metal impurity in other silicon is lower than that in lppmw. The average minority carrier lifetime ranges from 5.851 渭 s to 6.466 渭 s. The resistivity of the middle sample is within the range of 0.25 惟 cm-0.45 惟 路cm, and the resistivity of the edge sample is within the range of 0.15 惟 cm~0.5 惟 cm. In addition, the cutting position of the finished silicon ingot was calculated according to the impurity distribution formula. According to the calculated position, the yield of silicon ingot is directly increased by 3.5 ~ 4% compared with the original cutting position, and the output of single furnace (500kg) is increased by 15-20 kg.
【学位授予单位】:昆明理工大学
【学位级别】:硕士
【学位授予年份】:2015
【分类号】:TQ127.2
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