基于改进型Booth算法的大数乘法器的设计与验证

发布时间：2018-05-14 16:19

本文选题：改进型Booth算法 + 大数乘法器　；参考：《广西民族大学》2017年硕士论文

【摘要】：随着互联网技术不断发展,对Internet系统的攻击已经变得越来越复杂,而发动攻击所需要的技能与知识却下降了,攻击变得更自动化且所造成的破坏性也更大,信息安全问题日益突出。密码技术是保证信息安全的重要的核心技术。公钥密码技术得到了广泛应用,公钥密码所涉及的非对称的RSA算法成为研究的一个热点。加/解密的核心运算是对大数乘法器反复调用,它是运算最耗时且最关键的运算单元,其运行参数制约着加/解密芯片的主要性能指标,因此研究并设计低时延、并行、高效的乘法器对密码芯片设计的高效实现具有重大的现实意义。本文主要对Booth算法进行改进,对改进算法的乘法器进行n位扩展与FPGA设计实现,并对其进行软硬件正确性仿真验证。乘法器的实现基础是移位、编码、累加运算、位宽扩展等设计。因此,本文首先研究了常见各类加法器、Booth算法乘法器的设计方法、4-2压缩器原理及实现、乘法器结构研究及设计等。在Booth乘法器研究的基础上进行了一系列深入的研究,首先,基于Booth算法的基础上,提出了一种基于FPGA的创新型Booth算法,简化了Booth编码复杂性,减少了加法次数,仅需做一次加法运算,提高了运算速度;其次,在8位乘法器实现的基础上,进行位宽可扩展性设计,并提出了一种可扩展性的大数乘法器,并实现64位大数乘法器设计,可以应用于Montgomery算法的模乘、模幂调用的核心运算模块。提高了密码运算的速度,简化了设计方法。最后,对本文研究实现的内容与提出的创新的设计方法进行了软硬件仿真实验验证,在关键路径时延与消耗硬件资源方面进行了对比分析,并给出了对本文研究设计的总结与展望。
[Abstract]:With the development of Internet technology, attacks on Internet systems have become more and more complex, while the skills and knowledge required to launch attacks have declined, and attacks have become more automated and more destructive. The problem of information security is increasingly prominent. Cryptography is an important core technology to ensure information security. Public key cryptography technology has been widely used, the asymmetric RSA algorithm involved in public key cryptography has become a hot topic. The core operation of encryption / decryption is to call the multiplier of large numbers repeatedly. It is the most time consuming and key operation unit, and its operation parameters restrict the main performance index of encryption / decryption chip, so we study and design low delay and parallel. Efficient multiplier is of great practical significance to the efficient implementation of cipher chip design. In this paper, the Booth algorithm is improved, the multiplier of the improved algorithm is extended by n-bit and FPGA is designed and implemented, and the correctness of the multiplier is verified by software and hardware simulation. Multiplier implementation is based on shift, coding, cumulative operation, bit width expansion and other design. Therefore, this paper first studies the design method of the common adder, the principle and implementation of the 4-2 compressor, and the structure and design of the multiplier, etc. Based on the research of Booth multiplier, a series of deep research is carried out. Firstly, based on the Booth algorithm, an innovative Booth algorithm based on FPGA is proposed, which simplifies the complexity of Booth coding and reduces the number of additions. Only one addition operation is needed to improve the operation speed. Secondly, on the basis of the implementation of 8-bit multiplier, the bit width extensibility is designed, and a scalable large multiplier is proposed, and the design of 64-bit multiplier is realized. Can be applied to the Montgomery algorithm modular multiplication, modular power call the core operation module. It improves the speed of cryptographic operation and simplifies the design method. Finally, the contents of this paper and the innovative design methods are verified by software and hardware simulation experiments, and the critical path delay and the consumption of hardware resources are compared and analyzed. The summary and prospect of the research and design of this paper are also given.
【学位授予单位】：广西民族大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332.22

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