多核网络处理器共享存储控制系统设计与优化

发布时间：2018-10-09 09:34

【摘要】：本文针对片上多核网络处理器的结构对多核共享存储控制系统进行了设计与优化。主要设计完成了共享存储控制器片上接口队列结构、基于优先级的存储访问指令仲裁模块、多处理器与存储器进行数据交互的推拉引擎结构、存储控制器接口等核心模块功能。重点研究了共享存储控制器与多线程包处理引擎之间的异步访存方式、片上包缓冲结构RFIFO和TFIFO与存储控制器之间实现数据直接转发的DMA通道。考虑到对存储器长时间的访存延时，本文结合片上多核网络处理器对片外存储器充当转发表和数据包缓冲的需求，对共享存储控制器的结构进行了优化和改进，通过增加指令预取电路和对存储控制接口的改进可实现对SDRAM存储器的动态优化，根据连续指令地址信息动态选择同行同bank优化或bank交错优化方案，最大限度利用了可以优化的指令。最后并将共享存储控制系统的RTL级电路在XDNP多核网络处理器验证平台上进行了功能验证，结果表明控制的各个功能模块设计正确，能够完成多核处理器对片外SDRAM的访问。性能分析表明指令预取电路结构支持的动态优化方式比静态优化方式对存储器性能提升的效果更大。并且优化性能随着指令数的增加而增加，在连续执行指令数大于35以后，由于系统固有发送微包程序指令的限制系统性能提升效果达到稳定，，系统性能最大可以提升到45%。
[Abstract]:This paper designs and optimizes the multi-core shared storage control system for the multi-core network processor. The main functions of this paper are as follows: interface queue structure of shared memory controller, priority based memory access instruction arbitration module, push-pull engine structure of data interaction between multi-processor and memory, memory controller interface and other core module functions. The asynchronous memory access between the shared storage controller and the multithreaded packet processing engine is studied, and the DMA channel between the on-chip packet buffer structure (RFIFO) and the memory controller (TFIFO) is used to transmit the data directly. Considering the long time delay of memory access, this paper optimizes and improves the structure of shared memory controller by considering the demand of on-chip multi-core network processor to serve as forwarding table and packet buffer for off-chip memory. The dynamic optimization of SDRAM memory can be realized by adding instruction prefetching circuit and improving the memory control interface. According to the continuous instruction address information, we can dynamically select the peer optimization scheme with bank or bank interleaving optimization scheme. Maximize the use of optimizable instructions. Finally, the RTL level circuit of the shared memory control system is verified on the XDNP multi-core network processor verification platform. The results show that each functional module is designed correctly and the multi-core processor can access the off-chip SDRAM. The performance analysis shows that the dynamic optimization method supported by the instruction prefetching circuit structure is more effective than the static optimization mode in improving the memory performance. The optimization performance increases with the increase of the number of instructions. After the number of instructions is more than 35, the system performance can be improved to 45% because of the limitation of the inherent micropacket program instruction to improve the performance of the system.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TN47

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