面向并联机构的容错纠错实验研究

发布时间：2018-05-16 02:20

本文选题：容错 + 纠错　；参考：《电子科技大学》2011年硕士论文

【摘要】：容错纠错技术是提高机电产品安全性和可靠性的有效手段。本文以并联机构的容错纠错实验研究为主线,分别针对并联机构系统中的传感器故障、驱动器故障设计了容错纠错实验。第一个实验是基于工控机+运动控制卡的并联机构传感器故障的容错纠错实验;第二个实验是基于现场可编程门阵列(FPGA)的三自由度1PT+3TPS型并联机构的控制实验。此外还对并联机构驱动器故障的容错纠错方法和低密度奇偶校验(LDPC)纠错码进行了研究。基于并联机构的传感器故障容错纠错理论,针对三自由度1PT+3TPS并联机构实验平台,设计了传感器故障的容错纠错实验。采用运动控制卡+工控机作为实验控制器,首先实现了单个驱动器的PID控制实验,然后实现了针对并联机构平台传感器故障的容错纠错实验。实验结果表明当并联机构平台的传感器出现故障时,系统仍然能够连续正常运行,达到了对传感器故障的容错纠错目的。针对三自由度1PT+3TPS型并联机构运动平台,设计并实现了对该运动平台的手柄控制实验。选用FPGA作为实验中的控制器,采用verilog HDL语言实现了各个控制模块,详细介绍了该实验的各个模块的设计思想和实现技术。实验结果表明,当手柄运动到某一姿态时,通过对各条驱动腿的运动控制,1PT+3TPS型并联机构运动平台也运动到与之对应的姿态。针对1PT+3TPS并联机构的驱动器故障,提出了一种驱动器故障的容错纠错方法。当任一驱动器出现故障时,系统通过将中间从动腿转化为驱动腿,同时将故障驱动腿转化为从动腿,使得系统在驱动器出现故障时仍能连续正常运行,达到了对驱动器故障的容错纠错目的。文中给出了一个实例,来说明驱动器故障的容错纠错实现过程。对差错控制理论中的目前性能最接近香农限的纠错码——LDPC码进行了研究,针对LDPC码的编码复杂度高的问题,提出了一种稀疏生成矩阵的方法来降低编码复杂度。通过实例仿真证明该方法能对LDPC码编码复杂度降低30%左右,仿真结果也证明了该方法并不会降低LDPC码的性能。
[Abstract]:Fault - tolerant error correction technology is an effective means to improve the safety and reliability of mechanical and electrical products . In this paper , the fault - tolerant error correction experiment is designed based on the fault - tolerant error correction experiment of parallel mechanism . The first experiment is the fault - tolerant error correction experiment based on the parallel mechanism sensor of industrial control machine + motion control card . The second experiment is based on the control experiment of the three - degree - of - freedom 1PT + 3TPS type parallel mechanism of the field programmable gate array ( FPGA ) . In addition , the fault - tolerant error correction method and the low - density parity check ( LDPC ) error correction code of parallel mechanism driver failure are studied .

Based on the theory of fault tolerance and error correction of sensor fault in parallel mechanism , a fault - tolerant error correction experiment of sensor fault is designed aiming at three - degree - of - freedom 1PT + 3TPS parallel mechanism experiment platform . A motion control card + industrial control machine is used as the experimental controller . The fault - tolerant error correction experiment is realized for the fault of the parallel mechanism platform sensor . The experimental results show that when the sensor of the parallel mechanism platform fails , the system can run continuously and normally , and the fault - tolerant error - correcting purpose of the sensor fault is achieved .

In this paper , the control experiment of the handle of the three - degree - of - freedom 1PT + 3TPS parallel mechanism is designed and realized . Using FPGA as the controller in the experiment , each control module is realized by verilog HDL language . The experimental results show that when the handle moves to a certain attitude , the movement control of each driving leg is controlled , and the movement platform of the 1PT + 3TPS parallel mechanism is also moved to the corresponding posture .

In this paper , a fault - tolerant error - tolerant error - correcting method is presented for the fault of 1PT + 3TPS parallel mechanism . When any driver fails , the system is converted into the driving leg by converting the middle driven leg to the driven leg , while the fault - driving leg is converted into the driven leg , so that the fault - tolerant error - correcting purpose of the driver is achieved . An example is given to illustrate the fault - tolerant error - correcting realization process of the drive failure .

Aiming at the problem of high coding complexity of LDPC codes , a sparse generation matrix method is proposed to reduce coding complexity . Simulation results show that the method can reduce the coding complexity of LDPC codes by about 30 % , and the simulation results show that the method does not reduce the performance of LDPC codes .

【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2011
【分类号】：TH112

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