星载图像压缩系统中高速小波变换的FPGA设计与实现

发布时间：2018-06-06 18:15

本文选题：CCSDS图像压缩标准 + 多级二维小波变换　；参考：《中国科学院大学(中国科学院国家空间科学中心)》2017年硕士论文

【摘要】：随着成像技术的飞速发展,卫星图像的分辨率和数据率越来越高,数据量呈几何级增长,海量的图像数据占用了大量的储存容量和传输带宽。因此,为了降低星上数据缓存压力,减少对星地之间数据传输带宽的需求,研制一种高效的星载图像压缩编码系统十分必要。在现有的星载图像压缩系统中,基于DPCM以及DCT的编码算法压缩性能不高,基于DSP实现的算法处理速度较慢、功率消耗较大,FPGA虽然功耗较低,计算速度较快,但实现复杂的图像处理算法较为困难。为了解决这些问题,本文基于CCSDS 122.0-B-1图像压缩标准,提出了一种多级二维高速小波变换的硬件架构,并采用FPGA器件实现。本文主要工作为:(1)详细研究了CCSDS 122.0-B-1星载图像压缩标准中多级二维小波变换的算法,分析了其硬件可实现性以及一些影响性能的参数,并与其他图像压缩标准中的去相关算法进行了对比。(2)深入研究分析了二维小波变换的特点,并设计了合理的多级二维9/7小波变换以及5/3小波变换的硬件架构,具有变换速率高、外部资源占用较少、能够满足实时性要求等特点。(3)根据星载图像压缩系统的任务需求,提出了合理的硬件设计方案,并进行了相应的电路设计。(4)本文使用Verilog HDL语言对多级二维小波变换进行了实现,验证了所提出架构的正确性以及性能指标。并将小波变换与其他主流变换编码中的去相关方法进行了对比,同时对于9/7小波与5/3小波的去相关性能也进行了评估。实验结果表明,相对于传统的复用滤波器进行多级变换的结构,本文所提出的架构在FPGA逻辑资源允许的情况下,能够满足对图像进行实时变换的速度要求,降低片外RAM的使用需求,并为后续的数据编码和传输提供有利条件。
[Abstract]:With the rapid development of imaging technology, the resolution and data rate of satellite images are getting higher and higher, and the amount of data is increasing geometrically. Massive image data takes up a lot of storage capacity and transmission bandwidth. Therefore, in order to reduce the data cache pressure on the satellite and reduce the demand for data transmission bandwidth between the stars and ground, a kind of efficient satellite load is developed. The image compression coding system is very necessary. In the existing spaceborne image compression system, the compression performance based on DPCM and DCT is not high, the algorithm based on DSP is slow, the power consumption is large, the power consumption is low, and the computing speed is fast, but it is difficult to realize the complex image processing algorithm. In order to solve this problem, the algorithm is difficult to solve this problem. Some problems, based on CCSDS 122.0-B-1 image compression standard, a hardware architecture of multilevel two-dimensional high speed wavelet transform is proposed and implemented with FPGA devices. The main work of this paper is as follows: (1) the algorithm of multilevel two-dimensional wavelet transform in CCSDS 122.0-B-1 satellite image compression standard is studied in detail, and its hardware implementations and one are analyzed. Some parameters affecting the performance are compared with the other algorithms in the image compression standard. (2) the characteristics of the two-dimensional wavelet transform are studied and analyzed, and the hardware architecture of the reasonable multilevel two-dimensional 9/7 wavelet transform and the 5/3 wavelet transform is designed, which has high transformation rate, less external resources and can meet the real time property. Requirements and other characteristics. (3) according to the task requirements of the satellite borne image compression system, a reasonable hardware design scheme is proposed, and the corresponding circuit design is carried out. (4) this paper uses Verilog HDL language to implement the multilevel two-dimensional wavelet transform, verifies the correctness of the proposed architecture and the performance indicators. The correlation method in the transform coding is compared, and the correlation performance of the 9/7 wavelet and the 5/3 wavelet is also evaluated. The experimental results show that the proposed architecture can satisfy the real-time change of the image under the condition that the FPGA logical resource is allowed. The speed requirement of conversion can reduce the use requirement of off chip RAM and provide favorable conditions for subsequent data encoding and transmission.
【学位授予单位】：中国科学院大学(中国科学院国家空间科学中心)
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP391.41

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