基于可重构处理器的视觉信息主处理子系统研究

发布时间：2018-06-21 15:39

本文选题：可重构处理器 + 视觉信息处理　；参考：《天津大学》2016年硕士论文

【摘要】：可重构处理器兼具了ASIC方式的高效性和GPP方式的灵活性,可以很好地应用于计算量大但是并行化程度高的视频处理领域,充分发挥其并行计算高效性和可配置工作灵活性的优势。因此,利用可重构方式实现的视觉信息处理系统正逐渐成为一个新的研究热点。本文首先介绍了基于可重构处理器的视觉处理与演示系统的整体架构、系统的工作流程和数据流。随后介绍了视频采集子系统的结构和输出时序,论述了视频拼接主处理子系统与可重构处理器系统间图像数据和控制信息的传输方式。对主处理子系统进行了设计:包括I2C转PLB的桥接电路,实现了主处理系统和单片机的通信;PLB转UART的桥接电路,实现了主处理系统和后处理子系统的通信;对DDR读写电路进行设计,实现了视频数据缓存的功能。此外,本文将Retinex图像增强算法在可重构处理器模型上进行了映射分解,使其能够在通用可重构处理器上并行执行。同时,为了尽量减小计算量,本文提出了一种快速实现的随机喷洒Retinex图像增强算法,该算法在保证图像增强质量的同时,能够有效地提高算法执行效率。本文使用Modelsim软件对所设计的模块进行了仿真,同时基于FPGA开发板进行了功能验证。将Retinex图像增强算法在基于Soc Designer的可重构处理器仿真测试平台和基于Intel Atom 230的通用处理器测试平台上进行了串并行程序的性能分析与对比。实验结果表明,用并行流水方法实现的Retinex算法在程序执行效率上是传统串行方法的4.13倍,发挥了可重构处理器执行复杂图像处理算法时并行计算的优势。对于文中提出的快速实现随机喷洒Retinex算法(SRSR),基于MATLAB的仿真结果表明,SRSR相比于原始Retinex算法,图像的色彩系数、信息熵和标准差等指标基本一致,但算法运行速度提高了25.6倍,适用于有更高速度需求的领域。
[Abstract]:The reconfigurable processor has both the high efficiency of ASIC and the flexibility of GPP, so it can be used in the field of video processing with large amount of computation but high degree of parallelization. Give full play to its advantages of high efficiency of parallel computing and flexibility of configurable work. Therefore, the visual information processing system realized by reconfigurable mode is becoming a new research hotspot. This paper first introduces the architecture, workflow and data flow of the visual processing and demonstration system based on the reconfigurable processor. Then, the structure and output timing of video acquisition subsystem are introduced, and the transmission mode of image data and control information between video splicing main processing subsystem and reconfigurable processor system is discussed. The main processing subsystem is designed: including the bridge circuit of I2C to PLB, the bridge circuit between the main processing system and the communication between PLB and UART is realized, and the communication between the main processing system and the post-processing subsystem is realized. The DDR reading and writing circuit is designed to realize the function of video data cache. In addition, the Retinex image enhancement algorithm is mapped and decomposed on the reconfigurable processor model so that it can be executed in parallel on the general reconfigurable processor. At the same time, in order to minimize the computational complexity, this paper proposes a fast implementation of random spraying Retinex image enhancement algorithm, which can effectively improve the efficiency of the algorithm while ensuring the quality of image enhancement. This paper simulates the designed module with Modelsim software and validates the function based on FPGA development board. Retinex image enhancement algorithm is analyzed and compared on Soc designer based reconfigurable processor simulation and general processor test platform based on Intel Atom 230. Experimental results show that the Retinex algorithm implemented by parallel pipelining method is 4.13 times more efficient than the traditional serial method, and it takes advantage of parallel computing when the reconfigurable processor executes the complex image processing algorithm. The simulation results based on MATLAB show that compared with the original Retinex algorithm, the color coefficient, information entropy and standard deviation of the image are basically the same, but the speed of the algorithm is 25.6 times higher than that of the original Retinex algorithm. Suitable for areas with higher speed requirements.
【学位授予单位】：天津大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP391.41;TP332

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