HDR视频算法优化及硬件实现

发布时间：2018-07-26 09:09

【摘要】：高动态范围(high dynamic range,HDR)视频算法计算复杂度高,硬件实现需要大量逻辑和存储资源,且现有的算法难以满足高分辨率下的实时性要求.针对上述问题,提出一种优化的HDR视频流水线算法,同时利用FPGA的并行可重构特性,完成该算法的硬件实现.算法首先将相机响应函数内置于FPGA的查找表(look-up table,LUT)中,对3帧低动态范围(low dynamic range,LDR)图像进行合并,转换后的数据通过多路并行流水缓存在FPGA的BRAM中;然后使用快速的全局色调映射算法将结果实时显示输出.最终算法在Xilinx Kintex-7开发板上实验通过,在120MHz系统时钟频率下,对于1 920×1 080分辨率的视频流,处理速度达到65f?s,满足了实时性要求.
[Abstract]:High dynamic range (HDR) video algorithm has a high computational complexity, hardware implementation needs a lot of logic and storage resources, and the existing algorithms can not meet the real-time requirements of high resolution. In order to solve the above problems, an optimized HDR video pipeline algorithm is proposed. At the same time, the hardware implementation of the algorithm is accomplished by using the parallel reconfigurable feature of FPGA. First, the camera response function is built into FPGA lookup table (look-up table LUT), and three frames of low dynamic range (low dynamic range LDR images are merged, and the converted data is cached in FPGA BRAM through multichannel parallel pipeline. Then a fast global hue mapping algorithm is used to display the results in real time. Finally, the algorithm is tested on the Xilinx Kintex-7 development board. Under the clock frequency of the 120MHz system, the processing speed of the video stream with the resolution of 1,920 脳 10 080 can reach 65f / s, which meets the real-time requirements.
【作者单位】：中国科学院强耦合量子材料物理重点实验室(中国科学技术大学物理学院);国家专用集成电路设计工程技术研究中心合肥分中心;
【基金】：中国科学院战略性先导科技专项课题(XDA06010402-4)~~
【分类号】：TP391.41

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