小数分频锁相环设计及其杂散与噪声的抑制补偿

发布时间：2018-01-13 21:36

本文关键词：小数分频锁相环设计及其杂散与噪声的抑制补偿　出处：《国防科学技术大学》2014年硕士论文　论文类型：学位论文

【摘要】：集成电路技术迅猛发展,对数字芯片中时钟信号的品质要求越来越高。时钟信号的输出分辨率、相位噪声、变频时间等指标直接决定了整个时钟产生系统的性能好坏。小数分频型锁相环是实现高分辨率、快速变频时钟信号的常用结构,受到自身结构制约,小数分频锁相环不可避免的会引入大量杂散噪声。杂散噪声对输出信号影响极大,成为制约其应用的主要因素。在设计中消除和抑制杂散噪声成为挑战。本文主要关注如何优化锁相环的噪声性能,通过分析各种杂散与噪声的来源,提出对应的消除或者抑制方法。在设计中,尽可能的通过功能部件复用的方式,在不增加功耗情况下,通过使用抑制或者补偿锁相环噪声的技术,提高锁相环输出信号的抖动性能。本文的研究工作主要包括以下几个方面。(1)讨论了小数分频锁相环的基本结构,研究了杂散与噪声种类和来源,解释了杂散与噪声的产生机理。建立并分析小数分频锁相环的噪声模型。根据各种杂散对系统性能影响的特征,提出相对应的改善和抑制方式。分析环路带宽对于PLL整体噪声性能的影响,讨论环路带宽自适应技术的基本原理以及技术优势,设计了一种新型降低滤波电容的带宽自适应环路滤波电路。40nm与65nm两种工艺下的电路级仿真表明该锁相环性能稳定,证明了其性能对于工艺迁移不敏感。(2)设计了一款通用性好、高带宽、高分辨率、低抖动的小数分频锁相环。设计了一种提高线性度的电荷泵电路,通过在ΔΣ调制器最低位施加经过噪声整形的抖动信号,有效降低ΔΣ调制器自身引入的杂散噪声。研究基于DAC的噪声补偿技术,并通过动态元件匹配技术提高了DAC补偿的性能,使锁相环的噪声性能更加优化。设计了新型双级分频器,可以有效降低分频器的功耗,有利于降低锁相环整体功耗。(3)针对电路仿真速度慢的问题,设计基于AMS仿真器的Verilog-Spectre行为-晶体管级仿真模型,加速锁相环电路设计中的仿真验证速度,有效降低锁相环设计周期。在40nm CMOS工艺下实现了该锁相环版图设计,该PLL最小输出分辨率为0.048Hz,在3MHz频率偏差下的相位噪声为-130dBc/Hz,最大VCO输出频率达到3.2GHz,芯片面积为0.07mm2。带寄生参数的锁相环电路仿真性能良好,证明了本设计的通用性与高性能。
[Abstract]:With the rapid development of integrated circuit technology, the quality of clock signal in digital chip is becoming more and more high, the output resolution of clock signal and phase noise are becoming more and more important. Frequency conversion time and other indicators directly determine the performance of the whole clock generation system. Fractional frequency division type PLL is a common structure to achieve high resolution and fast frequency conversion clock signal, which is restricted by its own structure. The fractional frequency division PLL will inevitably introduce a large amount of stray noise, which has a great influence on the output signal. It is a challenge to eliminate and suppress the stray noise in the design. This paper focuses on how to optimize the noise performance of PLL, and analyzes the sources of all kinds of stray and noise. In the design, as far as possible through the functional component reuse, without increasing power consumption, through the use of phase-locked loop noise suppression or compensation technology. The research work of this paper mainly includes the following aspects: 1) the basic structure of fractional frequency division PLL is discussed, and the types and sources of spurious and noise are studied. The mechanism of spurious and noise generation is explained. The noise model of fractional frequency-division phase-locked loop is established and analyzed. According to the characteristics of various spurious effects on system performance. The influence of loop bandwidth on the overall noise performance of PLL is analyzed, and the basic principle and technical advantages of loop bandwidth adaptive technology are discussed. A novel bandwidth-adaptive loop filter circuit, which can reduce the filter capacitance, is designed. The circuit level simulation shows that the performance of the PLL is stable under the two technologies of 40nm and 65nm. It is proved that its performance is insensitive to process migration. (2) A kind of fractional frequency-division phase-locked loop with high bandwidth, high resolution and low jitter is designed, and a charge pump circuit is designed to improve the linearity. The noise compensation technique based on DAC is studied by applying noise shaping jitter signal at the lowest bit of 螖危 modulator to effectively reduce the stray noise introduced by 螖危 modulator itself. The performance of DAC compensation is improved by dynamic element matching technology, and the noise performance of PLL is optimized. A new two-stage frequency divider is designed, which can effectively reduce the power consumption of the divider. In order to reduce the overall power consumption of PLL, a Verilog-Spectre behavior-transistor level simulation model based on AMS simulator is designed to solve the problem of slow circuit simulation speed. The speed of simulation verification in the circuit design of PLL is accelerated, and the design cycle of PLL is reduced effectively. The layout design of PLL is realized in 40nm CMOS process. The minimum output resolution of the PLL is 0.048 Hz, the phase noise is -130 dBc / Hz at 3MHz frequency deviation, and the maximum VCO output frequency is 3.2 GHz. The chip area is 0.07mm2.The simulation performance of the PLL circuit with parasitic parameters is good, which proves the generality and high performance of this design.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

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