直接序列扩频信号窄带干扰抑制技术研究与实现

发布时间：2018-01-26 03:22

本文关键词： 直接序列扩频窄带干扰码辅助技术 FPGA　出处：《电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：凭借自身的抗干扰特性,直接序列扩频系统在现代通信中得到了广泛的应用。然而由于受到可用带宽、实现复杂度等条件限制,直扩系统的抗干扰能力终究有限。一旦干扰信号的功率超过了直扩系统的干扰门限,直扩系统的性能将恶化,甚至不能正常工作。论文研究了直扩信号的窄带干扰抑制技术,设计了三通道直扩信号的窄带干扰抑制方案,完成了干扰抑制软件的FPGA实现,并针对各项功能和指标,进行了详细的测试。全文主要工作如下:首先,设计了基于码辅助技术的三通道直扩信号窄带干扰抑制方案:(1)利用仿真验证了码辅助算法里分组长度M和干扰抑制性能的关系,确定了满足工程实现需求的分组长度M=12;(2)引入了延时分路,只增加很少的资源消耗,使得改进方案的干扰抑制性能比传统码辅助技术提高约0.6dB/Hz;(3)利用部分更新RLS算法,设计了三通道复用自相关矩阵更新模块的架构。与各通道独占自相关矩阵更新模块的架构相比,新架构降低资源消耗约60%,且干扰抑制性能无明显差异。其次,给出了三通道直扩信号窄带干扰抑制方案在FPGA上的详细设计。自顶向下设计了干扰抑制方案在FPGA上的实现细则,包括软件总体架构,子模块划分,接口定义和约束,以及主要模块的处理流程。最后,完成了三通道直扩信号窄带干扰抑制软件的性能测试。结果表明,干扰抑制软件实现了射频衰减控制和输出功率控制的功能;而且,在信号载噪比最低(56.5dB/Hz),干信比最强(单音34dB,窄带27dB)的情况下,经干扰抑制处理,达到了系统载噪比损失不超过2.5dB/Hz的要求,满足了I路误码率不超过81.0 10-′,Q路误码率不超过71.0 10-′的指标。本文设计的窄带干扰抑制软件,是作为独立模块加在直扩信号接收机前端的,并未影响现有接收机结构。在目前的直扩系统中,具有较强的可移植性和实用性。
[Abstract]:Direct sequence spread spectrum system (DSSS) has been widely used in modern communication due to its own anti-jamming characteristics. However, due to the available bandwidth, implementation complexity and other constraints. The anti-jamming ability of DSSS system is limited after all. Once the power of interference signal exceeds the interference threshold of DSSS system, the performance of DSSS system will deteriorate. This paper studies the narrowband interference suppression technology of DSSS signal, designs the narrowband interference suppression scheme of three-channel DSSS signal, and completes the FPGA implementation of interference suppression software. And according to the various functions and indicators, a detailed test. The main work of this paper is as follows: first. The narrow-band interference suppression scheme of three-channel direct spread spectrum signal based on code-assisted technique is designed. The simulation results show the relationship between block length M and interference suppression performance in the code-aided algorithm. The packet length M12 is determined to meet the requirements of engineering implementation. 2) the delay shunt is introduced, which only increases the resource consumption, and the interference suppression performance of the improved scheme is about 0.6 dB / Hz higher than that of the traditional code assistive technique. Using partial update RLS algorithm, this paper designs the architecture of three-channel multiplexing autocorrelation matrix updating module, which is compared with the architecture of each channel exclusive autocorrelation matrix update module. The new architecture reduces the resource consumption by about 60%, and there is no significant difference in the performance of interference suppression. The detailed design of the narrowband interference suppression scheme of three-channel direct spread spectrum signal on FPGA is given. The implementation details of the interference suppression scheme on FPGA are designed from top to bottom, including the overall software architecture and sub-module partition. Interface definition and constraint, as well as the processing flow of the main modules. Finally, the performance test of the three-channel direct spread spectrum signal narrowband interference suppression software is completed. The interference suppression software realizes the functions of RF attenuation control and output power control. Moreover, under the condition of the lowest signal-to-noise ratio of 56.5 dB / HzN and the strongest signal-to-interference ratio (single tone 34 dB, narrow band 27 dB), the interference suppression is carried out. The system can meet the requirement of loss of carrier to noise ratio less than 2.5 dB / Hz and the bit error rate of I is not more than 81.0 10'. The code error rate of Q channel is less than 71.0 10'. The narrowband interference suppression software designed in this paper is used as an independent module in the front end of the DSSS signal receiver. It does not affect the existing receiver structure. It has strong portability and practicability in the current DSSS system.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.4

【参考文献】