基于FPGA的准循环LDPC码硬件仿真设计与实现

发布时间：2018-01-26 22:42

本文关键词： 准循环LDPC码编码器分层译码器高斯白噪声 TDMP FPGA　出处：《北京邮电大学》2015年硕士论文　论文类型：学位论文

【摘要】：自从上世纪90年代开始,LDPC码重新引起了人们的重视。由于其性能接近香农极限,LDPC码已经广泛应用于DVB-S2、CMMB、4G通信系统、卫星通信和数字水印系统。目前,在航天领域的多个预研项目中,都在论证采用LDPC码提高系统性能的可行性。 LDPC码的优化设计是一项复杂的工作,每优化出一个码都需要对其性能进行仿真评估。很多应用场景对LDPC的错误平层有较高要求,仿真需要达到10-7以下的误比特率,因此仿真的数据量至少要达到109比特,对如此大量的数据进行软件仿真必然需要耗费大量的计算时间。本文试图基于FPGA设计一款针对准循环LDPC码的硬件仿真器,能够在很短的时间内实现对于某种LDPC码性能的仿真评估。围绕LDPC码硬件仿真器设计这一目标,本文主要完成了以下工作。首先,研究了基于准循环生成矩阵的QC-LDPC码的编码算法和其SRAA电路实现原理,重点研究了基于准循环校验矩阵的编码算法,通过利用其双对角线化结构特征推导出校验比特的迭代计算公式,在FPGA平台上实现了高吞吐率编码。其次,研究和比较了多种不同的译码算法的性能、迭代收敛速度及其实现方法,重点研究了结构化的QC-LDPC码的分层译码算法,并在FPGA平台上实现了基于这种算法的通用译码器。最后,设计了外围的随机数据源模块、映射模块、软解调模块、高斯白噪声发生器模块和误码率统计模块,与准循环LDPC编码器和译码器一起构成了准循环LDPC码硬件仿真器,可以通过配置不同校验矩阵参数和噪声方差,实现大量数据的快速仿真。
[Abstract]:Since -10s, LDPC codes have attracted more and more attention. Since their performance is close to the Shannon limit, LDPC codes have been widely used in DVB-S2CMB. 4G communication system, satellite communication and digital watermarking system. At present, the feasibility of using LDPC code to improve system performance is demonstrated in many pre-research projects in aerospace field. The optimal design of LDPC codes is a complex task, each optimization of a code needs to be evaluated by simulation. Many application scenarios have higher requirements for the error level of LDPC. Simulation needs to achieve a bit error rate below 10-7, so the amount of data must be at least 109 bits. Software simulation of such a large amount of data is bound to cost a lot of computing time. This paper attempts to design a hardware simulator for quasi-cyclic LDPC code based on FPGA. The performance of a certain LDPC code can be evaluated in a very short time. Focusing on the design of LDPC code hardware simulator, this paper mainly completes the following work. First of all. The coding algorithm of QC-LDPC code based on quasi-cyclic generation matrix and its realization principle of SRAA circuit are studied, and the coding algorithm based on quasi-cyclic check matrix is studied emphatically. By using its dual diagonal linearized structure feature, the iterative calculation formula of the check bit is deduced, and the high throughput coding is realized on the FPGA platform. Secondly, the performance of different decoding algorithms is studied and compared. The iterative convergence rate and its implementation method are discussed. The hierarchical decoding algorithm of structured QC-LDPC codes is studied, and a general decoder based on this algorithm is implemented on the FPGA platform. Finally. The peripheral random data source module, mapping module, soft demodulation module, Gao Si white noise generator module and error rate statistics module are designed. A hardware simulator for quasi-cyclic LDPC codes is constructed with quasi-cyclic LDPC encoders and decoders. The fast simulation of a large number of data can be realized by configuring different parameters of check matrix and noise variance.
【学位授予单位】：北京邮电大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.22

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