基于高级综合的CABAC的VLSI设计

发布时间：2018-02-08 22:58

本文关键词： 高清分辨率 CABAC HLS 流水　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：随着信息化时代的到来,越来越多的高清分辨率甚至超清分辨率的视频出现在人们的生活中,实时对这类视频进行压缩并传输的需求也越来越多。2013年1月JCT-VC发布了最新的视频压缩标准HEVC。该标准采用了基于四叉树的编码组织结构以及更大尺寸的编码块,加入了更多的预测方向,其压缩效率比现有的H.264标准高了一倍。HEVC标准采用基于上下文模型的二进制算术编码(Context-based Adaptive Binary Arithmetic Coding,CABAC)作为其熵编码的编码算法。CABAC在HEVC中的作用非常重要,它根据精确的上下文概率模型对残差信息进行编码,达到了接近香农熵的编码性能。但是由于CABAC的工作模式为串行逐比特编码,使得它成为了HEVC视频压缩的主要瓶颈。赛灵思公司近年来新推出的高级综合工具(High-Level-Synthesis,HLS),它帮助工程师隐藏了寄存器转换级(Register Transfer Lever,RTL)设计和现场可编程逻辑器件(Field-Programmable Gate Array,FPGA)结构的细节,其验证过程也较为简单,能够大幅地减少硬件系统的开发周期。为了解决CABAC吞吐率瓶颈的问题,本文在仔细研究了HEVC标准和CABAC算法原理的基础上,从算法上分析CABAC的速度瓶颈,并且使用HLS工具进行CABAC的硬件设计实现。本文的主要工作有:1.提出了一种多级流水的CABAC实现架构。将CABAC划分成比特编码、码流打包和码流输出三个子模块,通过分支预测技术去除了比特编码模块和码流输出模块之间的数据相关性,在三个模块间建立起多级流水线,提高了CABAC的数据吞吐率。2.利用HLS工具完成了满足4K实时视频编码的CABAC实现。针对提出的CABAC的硬件架构,利用HLS工具分别对CABAC的常规编码模式和旁路编码模式进行实现和相应优化;通过partition约束将数组映射为寄存器以提高数据访问速度,通过unroll约束将串行执行的循环体映射为并行执行的循环体以缩短处理时延;通过pipeline约束在多个模块间建立流水线以最终实现一种多级流水的可实时编码的CABAC的硬件架构;最后将所设计的CABAC编码器架构利用HLS工具进行RTL功能仿真。本文针对HEVC中CABAC的硬件实现,提出了一种多级流水的硬件架构,并通过HLS工具实现。实验结果表明,该架构能够获得比较高的数据吞吐率,满足4K分辨率视频实时压缩的需求。本文所提出的CABAC编码器的核心架构,其算法复杂度低,可通过单片FPGA实现,具有很高的实际应用价值。
[Abstract]:With the advent of the information age, more and more high-definition and even super-resolution video appear in people's lives. In January 2013, JCT-VC released the latest video compression standard, HEVC, which uses a quadtree based coding organization and larger coding blocks. By adding more prediction directions, its compression efficiency is twice as high as the existing H.264 standard. The Contex-based Adaptive Binary Arithmetic coding algorithm, named Contex-based Adaptive Binary Arithmetic coding algorithm, is used as the coding algorithm in HEVC. It is very important for the HEVC standard to use the Context-based Adaptive Binary Arithmetic coding method as its coding algorithm. It encodes the residual information according to the accurate context probability model, which achieves the coding performance close to Shannon entropy. However, because the CABAC work mode is serial bit by bit coding, It has become a major bottleneck in HEVC video compression. The company's new advanced integration tool, High-Level-Synsissis, has helped engineers hide the details of the register-conversion level Register Transfer ever#en0# design and the Field-Programmable Gate ArrayFPGA architecture. In order to solve the bottleneck problem of CABAC throughput, this paper analyzes the speed bottleneck of CABAC on the basis of studying the HEVC standard and the principle of CABAC algorithm. The main work of this paper is: 1. A multilevel income CABAC implementation architecture is proposed. The CABAC is divided into three sub-modules: bit coding, bitstream packaging and stream output. The data correlation between the bit-coding module and the bit-stream output module is removed by the branch prediction technology, and a multi-level pipeline is established among the three modules. The data throughput of CABAC is improved. 2. The implementation of CABAC for 4K real-time video coding is accomplished by using HLS tools. The hardware architecture of CABAC is proposed. The conventional encoding mode and bypass coding mode of CABAC are realized and optimized by using HLS tool, and the array is mapped to register by partition constraint to improve the data access speed. The serial execution loop body is mapped to the parallel execution loop body by unroll constraint to shorten the processing delay, pipeline is set up among several modules by pipeline constraint to realize a multistage income real-time encoding CABAC hardware architecture. Finally, the designed CABAC encoder architecture is simulated with HLS tools for RTL function. Aiming at the hardware implementation of CABAC in HEVC, a kind of multilevel income hardware architecture is proposed and implemented by HLS tool. The experimental results show that, This architecture can achieve high data throughput and meet the demand of real-time video compression with 4K resolution. The core architecture of CABAC encoder presented in this paper has low algorithm complexity and can be realized by single chip FPGA. It has high practical application value.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81

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