基于TMS320C6678的多核DSP并行处理应用技术研究

发布时间：2018-02-27 01:18

本文关键词： TMS320C6678 并行处理 FFT 合成孔径雷达　出处：《北京理工大学》2014年硕士论文　论文类型：学位论文

【摘要】：随着雷达成像技术的不断发展，对成像范围、成像精度和处理实时性的要求越来越高，这就提出了对更大数据量、运算量和成像速度的需求，一般情况下的采用单核DSP完成计算已经不能满足这方面需求的变化，多核DSP并行处理成为发展的趋势，业内关于TMS320C6678多核DSP芯片的研究已经进行了一段时间，对TMS320C6678芯片针对雷达信号处理的并行开发显得尤为重要。本文主要内容包括： 1.研究了TMS320C6678的Keystone多核架构和内核结构以及实验室开发的基于C6678的4DSP通用处理平台，主要研究了C6678芯片中雷达信号处理实现中常用的SRIO接口、Hyperlink接口和EDMA3数据交互技术、常用的同步技术基于C6678的实现方案。 2.针对SAR成像的主要运算FFT，研究了可进行并行任务划分的基于二维矩阵的FFT算法，在C6678片上小内存的限制下，设计并行时序，利用多核联合处理实现了超长点数FFT运算，包括基于C6678共享空间的单片并行处理和基于Hyperlink接口的多片并行处理，单片多核并行处理相较于单核处理效率基本实现线性提升，，多片联合处理实现了小内存空间限制下的更大点数FFT。 3.针对二维拆分FFT算法中的多核并行处理过程进行优化，包括了基于共享内存的多核同步优化，相较于常规的同步技术，速度提升5倍以上。基于铰链因子的内存优化，只存储一行铰链因子，通过其规律辅助计算其他铰链因子，减小占用内存空间百倍以上。基于双缓冲区的并行优化，将数据IO与内核计算并行，进一步缩短FFT计算时延。 4.设计了SAR雷达CS算法基于通用处理平台的实现方案，应用二维FFT多核并行处理算法，多核数据存储技术和三角函数查表技术等，对CS算法的实现针对常规回波矩阵和大回波矩阵进行了并行设计。
[Abstract]:With the continuous development of radar imaging technology, the requirements of imaging range, imaging accuracy and real-time processing are becoming higher and higher. In general, the use of single core DSP to complete computing has not been able to meet the change of requirements in this respect, and the parallel processing of multi-core DSP has become a trend of development. The research on TMS320C6678 multi-core DSP chips has been carried out for some time in the industry. The parallel development of TMS320C6678 chip for radar signal processing is particularly important. The main contents of this paper are as follows:. 1. The Keystone multi-core architecture and kernel structure of TMS320C6678 and the 4DSP general processing platform based on C6678 developed by the laboratory are studied. The SRIO interface and EDMA3 data interaction technology which is commonly used in radar signal processing in C6678 chip is mainly studied. The commonly used synchronization technology is based on the implementation of C 6678. 2. Aiming at the main operation of SAR imaging, the FFT algorithm based on 2-D matrix, which can be divided into parallel tasks, is studied. Under the limitation of small memory on C6678 chip, the parallel timing is designed, and the super-long FFT operation is realized by using multi-core joint processing. It includes single chip parallel processing based on C6678 shared space and multi chip parallel processing based on Hyperlink interface. Compared with single core processing, the efficiency of single chip multi core parallel processing is improved linearly. Multi-chip joint processing implements a larger number of FFTs under the limitation of small memory space. 3. The multi-core parallel processing process in the two-dimensional split FFT algorithm is optimized, including the multi-core synchronization optimization based on shared memory. Compared with the conventional synchronization technology, the speed is more than five times faster. Only a single line of hinge factors is stored, and the other hinge factors are calculated by its rule, which reduces the memory space by more than 100 times. Based on the parallel optimization of double buffers, the data IO is paralleled with the kernel computation to further shorten the computing delay of FFT. 4. The realization scheme of SAR radar CS algorithm based on general processing platform is designed. Two dimensional FFT multi-core parallel processing algorithm, multi-core data storage technology and trigonometric function look-up table technology are applied. The implementation of CS algorithm is designed in parallel for conventional echo matrix and large echo matrix.
【学位授予单位】：北京理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.52

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