高性能图像压缩芯片的验证和测试

发布时间：2018-03-15 01:12

本文选题：功能验证　切入点：静态时序分析　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：随着我国航天事业的不断蓬勃发展,新型航天器所获得的图像数据量越来越大,这给星上数据存储带来了困难,也给传输信道造成繁重负担。图像压缩系统作为星载数传系统的重要组成部分,能有效的对数据进行压缩。采用高性能图像压缩芯片有利于系统的实现,也有利于提高系统的稳定性,同时使得系统具有实时压缩图像数据的能力。本课题组承担的某型号高速图像压缩芯片以JPEG2000为核心算法,支持无损压缩和有损压缩,最高工作频率为210MHz,最高处理速率大于105MSamples/s。该芯片采用了130nm工艺生产,规模4千多万门。该图像压缩芯片具有高处理速率、低功耗、抗辐照等优点,为航天航空发展需要的专用元器件,符合我国航天航空器件高可靠高性能的要求。本论文主要研究了该芯片的验证测试工作,包括功能验证、静态时序分析、时序仿真和单粒子效应模拟实验。功能验证主要针对芯片压缩核、外挂存储器、配置接口、相机接口、码流输出接口、芯片工作频率以及异步时序等展开。不同的验证选取不同的针对性向量进行测试。对于接口,以分析其接口时序为主,保证其符合芯片接口规范。静态时序分析通过PrimeTime抽取整个电路的所有同步时序路径,根据路径的门延时和线延时计算每条路径的总延时,最终得到了完整的静态时序报告。根据静态时序报告,分析和优化存在时序违例的关键路径。时序仿真使用网表与时序约束文件,通过时序仿真验证平台,完成了PLL工作时序、相机接口时序、码流输出接口时序、SDRAM接口时序、异步时序等验证工作。根据单粒子辐照实验要求,搭建了以FPGA为核心的自动化测试平台,实现了自动发送图像、自动比对、实时显示以及实时存储等功能。实验过程中使用多种粒子分别对两块芯片进行了测试,实验结果显示,一期芯片存在单粒子锁定敏感的问题,二期芯片由于采用了新的工艺,解决了单粒子锁定的问题。
[Abstract]:With the rapid development of the space industry in our country, the amount of image data obtained by the new spacecraft is increasing, which makes it difficult to store the data on board. As an important part of spaceborne data transmission system, image compression system can compress data effectively. Using high performance image compression chip is beneficial to the realization of the system. It is also helpful to improve the stability of the system and make the system have the ability to compress image data in real time. The core algorithm of a certain type of high-speed image compression chip is JPEG2000, which supports lossless compression and lossy compression. The highest working frequency is 210MHz, and the highest processing rate is more than 105MSamples / s. The chip is manufactured by 130nm process and has a scale of more than 4,000 gates. The image compression chip has the advantages of high processing rate, low power consumption, irradiating resistance and so on. The special components for aerospace development meet the requirements of high reliability and high performance of aerospace devices in China. This paper mainly studies the verification and testing work of this chip, including function verification, static timing analysis. Timing simulation and single particle effect simulation experiment. Function verification is mainly for chip compression core, external memory, configuration interface, camera interface, bitstream output interface, Chip frequency and asynchronous timing expansion. Different validation selected different targeted vectors for testing. For the interface, mainly to analyze its interface timing, The static timing analysis extracts all synchronous sequential paths of the whole circuit through PrimeTime, and calculates the total delay of each path according to the gate delay and line delay of the path. Finally, the complete static timing report is obtained. According to the static timing report, the critical path of timing violation is analyzed and optimized. The timing simulation uses the network table and timing constraint file, and completes the PLL working timing through the timing simulation verification platform. Camera interface timing, bitstream output interface timing, SDRAM interface timing, asynchronous timing, etc. According to the requirements of single particle irradiation experiment, an automatic test platform based on FPGA is built, which can automatically send images and compare them automatically. Real time display and real time storage are used to test the two chips. The experimental results show that the first stage chip has the problem of single particle locking sensitivity, and the second phase chip has adopted a new technology. The problem of single particle locking is solved.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：V557;TN919.81

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