锁相环中PFD和CP的设计

发布时间：2018-03-29 09:20

本文选题：电荷泵锁相环频率综合器　切入点：鉴频鉴相器　出处：《东南大学》2014年硕士论文

【摘要】：据不完全统计,人们所获取的信息有80%以上是通过视觉器官得到的。随着半导体技术的不断提高,图像传感器因其能实现图像信息的获取、转换和扩展,而得到越来越广泛的应用。高集成度低功耗的互补金属氧化物半导体图像传感器(CMOS Image Sensor, CIS)逐渐取代电荷耦合元件图像传感器(CCD Image Sensor, CCD)成为图像传感器的主流器件,电荷泵锁相环频率综合器.(Charge Pump Phase Locked Loop frequency synthesizer, CPPLL)以其低功耗、高速、低抖动和低成本的优势在CIS中得到广泛的应用,作为其中的关键模块鉴频鉴相器(Phase Frequency Detector, PFD)和电荷泵(Charge Pump, CP),前者决定了系统的精度和稳定度,而后者为系统提供了宽的频率捕捉范围和快速的锁定能力。本文首先介绍CP PLL的项目背景；然后分析了CP PLL的特点,阐述了CP PLL中关键模块PFD以及CP的工作原理和结构分类；接着详细讨论了PFD和CP的设计指标以及设计中的难点问题,通过基于TSPC (True Single Phase Clock, TSPC)动态D触发器式高精度PFD,以及结合宽输入范围误差运放和自偏置共源共栅电流镜结构的CP的设计,实现了电荷泵充放电流的高精度宽范围匹配的设计要求;最后本文在0.13μm CMOS工艺下完成了PFD和CP模块的版图设计和优化,并对电路进行了流片验证。测试结果表明：在1.8V电源电压下,PFD的各种逻辑功能均正确；CP在0.3V-1.7V的输出电压范围内工作电流基本稳定在100μA,在0.4V-1.7V的电压范围内,失配电流小于0.4μA,PFD和CP总的功耗为7.2mmW。作为图像信息领域的一个研究热点,开发与CIS相关的高性能PFD和CP芯片具有重要的研究价值和市场应用前景,本课题设计的PFD和CP已成功应用于CIS芯片中。
[Abstract]:According to incomplete statistics, more than 80% of the information obtained by people is obtained through visual organs. With the continuous improvement of semiconductor technology, image sensors can achieve the acquisition, conversion and expansion of image information. The complementary metal oxide semiconductor image sensor with high integration and low power consumption has gradually replaced the charge coupled element image sensor (CCD-CCD Image sensor) as the mainstream device of the image sensor. Charge Pump Phase Locked Loop frequency synthesizer (CPPLL) is widely used in CIS with its advantages of low power consumption, high speed, low jitter and low cost. As a key module, the phase Frequency detector (PFDs) and the charge pump charge pump (PFDs) determine the accuracy and stability of the system. The latter provides the system with wide frequency capture range and fast locking capability. Firstly, this paper introduces the project background of CP PLL, then analyzes the characteristics of CP PLL, and expounds the working principle and structure classification of the key module PFD and CP in CP PLL. Then, the design index of PFD and CP and the difficult problems in the design are discussed in detail. Based on TSPC true Single Phase lock (TSPC) dynamic D flip-flop high precision PFDs, and the design of CP with wide input range error operational amplifier and self-bias CSM structure, the design of CP-FDs based on dynamic D flip-flop is presented. The design requirements of charge pump charge-discharge flow with high precision and wide range matching are realized. Finally, the layout design and optimization of PFD and CP modules are completed in 0.13 渭 m CMOS process. The test results show that all logic functions of the circuit are correct at 1.8 V power supply voltage. The current working current is basically stable at 100 渭 A in the output voltage range of 0.3V-1.7V, and is within the voltage range of 0.4V-1.7V. The total power consumption of the mismatched current is less than 0.4 渭 An PFD and CP is 7.2 mmW. as a research hotspot in the field of image information, the development of high-performance PFD and CP chips related to CIS has important research value and market application prospect. The PFD and CP designed in this paper have been successfully applied to CIS chip.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

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