应用于时钟发生器的延迟锁相环的设计

发布时间：2018-05-18 03:46

本文选题：延迟锁相环 + 折叠运放　；参考：《南京邮电大学》2015年硕士论文

【摘要】：延迟锁相环是时钟发生器电路的一个重要部分。相比于锁相环,延迟锁相环内用压控延迟线代替压控振荡器,其时钟抖动更低,系统更加稳定,因而应用前景更加广泛。本文对延迟锁相环电路的国内外研究现状进行了调研,并对其系统及各主要模块的工作原理进行了深入研究和分析,在此基础上设计了一种可以应用于时钟发生器的高频率、低抖动性能的延迟锁相环。本文设计的延迟锁相环主要部分为五个模块:鉴相器、电荷泵、滤波器、压控延迟线和偏置部分。鉴相器采用了动态D触发器,实现了低功耗,解决了鉴相器中存在的鉴相死区和工作速度慢的问题,并且针对于实际锁定时输出时钟波形的毛刺现象,提出在鉴相器两个输入端加入反相器进行隔离,从而抑制了系统输出时钟的毛刺。电荷泵懫用折叠运放实现了充放电电流的良好匹配,有效减小了系统的抖动。压控延迟线采用了自偏置结构的差分可控电流源型延迟单元,抑制共模噪声的同时减小了系统的抖动,此外还采用低压差线性稳压器进行供电,减小了电源电压波动对于延迟时间的影响以及系统的抖动。滤波器由分压电路产生初始电压,该分压电路由起始电路控制,也可以由外接的芯片开关控制,从而可以避免系统发生错误锁定。本文设计的延迟锁相环基于SMIC 0.18μm CMOS工艺进行设计,并通过Spectre仿真器对各个模块电路以及系统电路进行仿真。实验结果表明电源电压为1.8V时,电路工作频率范围从500MHz到750MHz。当输出时钟为500MHz时,均方根抖动0.576ps,峰峰抖动为7.331ps,功耗约为1.72mw;当输出时钟为750MHz时,均方根抖动为0.332ps,峰峰抖动为4.225ps,功耗约为3.36mw。
[Abstract]:Delay phase locked loop (DPLL) is an important part of clock generator circuit. Compared with the phase-locked loop, the voltage-controlled delay line is used to replace the voltage-controlled oscillator in the delay PLL, the clock jitter is lower, the system is more stable, and the application prospect is more extensive. In this paper, the domestic and international research status of delay phase-locked loop circuit is investigated, and the working principle of its system and main modules is deeply studied and analyzed. On the basis of this, a kind of high frequency which can be applied to clock generator is designed. Low jitter performance delay PLL. There are five modules in this paper: phase detector, charge pump, filter, voltage-controlled delay line and bias part. Dynamic D flip-flop is used in the phase detector, which realizes low power consumption, solves the problems of phase dead zone and slow working speed in the phase discriminator, and aims at the burr phenomenon of the output clock waveform when the phase detector is actually locked. In order to restrain the burr of the output clock, the inverter is added to the two input terminals of the phase detector to isolate the phase detector. The charge pump realizes the good match of charge and discharge current by folding operational amplifier, and effectively reduces the jitter of the system. The voltage-controlled delay line uses a self-biased differential controllable current source type delay unit to suppress common mode noise and reduce the system jitter. In addition, a low-voltage differential linear regulator is used to supply the power. The effect of voltage fluctuation on delay time and system jitter is reduced. The initial voltage of the filter is generated by the divider circuit, which can also be controlled by an external chip switch to avoid the system error locking. The DPLL designed in this paper is based on the SMIC 0.18 渭 m CMOS process, and simulates each module circuit and the system circuit through the Spectre simulator. The experimental results show that the operating frequency range of the circuit is from 500MHz to 750 MHz when the supply voltage is 1.8 V. When the output clock is 500MHz, the root mean square jitter is 0.576psand the peak jitter is 7.331ps.The power consumption is about 1.72mw. when the output clock is 750MHz, the root-mean-square jitter is 0.332ps, the peak jitter is 4.225psand the power consumption is about 3.36mw.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.8

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