应用于数字电源控制器的模数转换器的设计

发布时间：2018-05-20 09:23

本文选题：数字电源控制器 + 模数转换器　；参考：《复旦大学》2014年硕士论文

【摘要】：目前数字电源在手机、平板电脑、音乐播放器等电子设备中的应用越来越广泛。相比模拟电源,数字电源具有功耗低、鲁棒性强、方便集成、控制算法多样、可编程等诸多优势。而在数字电源控制器中,模数转换器(Analog to Digital Converter, ADC)替代了模拟电源中的误差放大器,在数字电源中发挥关键作用。如何在保证ADC性能的前提下,降低其功耗和面积,成为一个重要课题。本论文首先介绍了数字电源与模拟电源的基本原理,并对二者进行对比,总结出数字电源相比于模拟电源的优势。然后介绍了在数字电源控制器中较为流行的几种ADC架构,进而总结出不同ADC架构的优缺点,以及数字电源系统对ADC的要求。基于数字电源系统的要求,本文提出一种新的ADC架构——脉宽调制型ADC,采用电压-时间,时间-数字两步转换的方法完成模拟电压到数字信号的转换。该ADC通过与数字脉宽调制器(Digital Pulse Width Modulator, DPWM)拙用延迟锁定环(Delay Locked Loop, DLL),节省了数字电源系统的功耗和面积。本文通过对共用DLL技术的分析,总结出了这一技术面临的难点和挑战。该ADC的设计有效位为8bit,采样频率为1 MS/s。在具体的电路设计中,重点对斜波信号发生器、比较器、时间数字转换器(Time to Digital Converter, TDC)模块进行了设计与仿真。在斜波信号发生器的设计中,通过使用电流舵技术,兼顾功耗的同时,提高了斜波线性度；比较器采用轨到轨的静态比较器,保证在规定的输入摆幅内,比较器可以保持比较固定的失调：时间数字转换器采用计数器和延迟链两步量化的结构,并通过逻辑优化,保证了粗细量化的同步与匹配；在版图设计中,重点解决了模拟数字隔离、比较器对称、天线效应等问题。芯片最终在SMIC 0.13μmCMOS工艺下流片,并制作PCB板对芯片进行测试。芯片面积仅为0.03 mm2,功耗仅为60μW；积分非线性(Integral Nonlinearity,INL)为-0.5 LSB～1 LSB,微分非线性(Differential Nonlinearity, DNL)为-1 LSB-0.5LSB,单调性良好；信号噪声失真比(Signal to Noise and Distortion Ratio, SINAD)为42.1dB,有效位6.7位。整体测试结果符合系统要求,同时也较好的实现了低功耗和低面积的设计目标,ADC与DPWM共用DLL技术得到了验证。
[Abstract]:At present, digital power is more and more widely used in mobile phone, tablet computer, music player and other electronic devices. Compared with analog power supply, digital power supply has many advantages, such as low power consumption, strong robustness, convenient integration, various control algorithms, programmable and so on. In the digital power supply controller, the analog-to-digital converter Analog to Digital Converter, ADC) replaces the error amplifier in the analog power supply and plays a key role in the digital power supply. How to reduce the power consumption and area while ensuring the performance of ADC has become an important issue. In this paper, the basic principles of digital power supply and analog power supply are introduced, and compared with each other, the advantages of digital power supply compared with analog power supply are summarized. Then several popular ADC architectures in digital power supply controller are introduced, and the advantages and disadvantages of different ADC architectures are summarized, as well as the requirements of digital power supply system for ADC. Based on the requirement of digital power supply system, this paper presents a new ADC architecture, which uses voltage-time, time-digital two-step conversion to complete the conversion of analog voltage to digital signal. This ADC can save the power and area of the digital power supply system by using delay Locked Loop, DLLL, delay locking loop and digital pulse width modulator digital Pulse Width Modulator, DPWM). Based on the analysis of common DLL technology, the difficulties and challenges faced by this technology are summarized in this paper. The designed effective bit of the ADC is 8 bit and the sampling frequency is 1 MS / s. In the specific circuit design, the design and simulation of oblique wave signal generator, comparator and time digital converter (TDC) time to Digital Converter, TDC) module are emphasized. In the design of oblique wave signal generator, the current rudder technology is used to improve the linearity of oblique wave while taking into account the power consumption, and the comparator adopts a static comparator from rail to ensure that it is within the prescribed input swing. The comparator can keep the fixed misalignment: the time-digital converter adopts the structure of counter and delay chain two-step quantization, and through the logic optimization, ensures the synchronization and matching of the coarse quantization. The problems of analog digital isolation, comparator symmetry and antenna effect are solved. Finally, the chip is downflow in SMIC 0.13 渭 mCMOS process, and the PCB board is made to test the chip. The chip area is only 0.03 mm ~ 2, the power consumption is only 60 渭 W, the integral nonlinear integral linearity INLL) is -0.5 LSB~1 LSBs, the differential nonlinear linearity (DNL) is -1 LSB-0.5 LSB-0.5LSB.The signal noise distortion ratio is 42.1 dB, and the effective bit is 6.7 bits. The overall test results meet the requirements of the system. At the same time, the low power consumption and low area ADCs and DPWM common DLL technology are well realized.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN792;TN86

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