HEVC帧内预测单元的硬件设计

发布时间：2018-06-01 14:58

本文选题：HEVC + 帧内预测　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：视频作为多媒体信息的重要组成部分,近年来呈现出以超高分辨率为特征的新趋势,而以宏块为基础的H.264/AVC压缩标准却越来越难以满足高清和超高清视频的压缩需求。为适应超高分辨率视频的压缩需求,国际电联和国际标准化组织共同提出了HEVC视频压缩标准,其压缩效率相比于H.264/AVC提高了近一倍。但是算法改进的同时也引起了复杂度的提升,这也给实时编码器的设计带来了巨大的挑战。由于FPGA在数据的处理速度上有着通用处理器无法比拟的巨大优势,因此对算法尤其是帧内预测算法的硬件化设计成了近年来研究的热点。此外,利用Xilinx公司推出的Vivado-HLS工具能将软件代码描述的硬件电路进行RTL级的综合实现和验证,与传统的基于Verilog/VHDL等硬件描述语言的硬件开发相比,使用HLS工具能够方便的对模块的设计架构进行不断地迭代优化,从而极大地缩短了硬件设计开发的周期,这也逐渐成为了FPGA开发的新方式。本文首先介绍了HEVC帧内预测的算法,然后根据帧内预测中参考点预处理模块和粗选模块的特点设计了适合硬件实现的流水和并行架构:(1)参考点预处理模块的流水设计。HEVC标准软件中预处理算法的可用性判断、赋值和平滑是串行处理的。模块的时钟延迟很大,吞吐率不高,为降低延迟和提高吞吐率,设计了一种预处理模块的流水结构,使其数据吞吐率相比于标准算法的串行缓存结构提高了四倍。(2)粗选单元模块的并行化设计。基于粗选模块中存在的并行特性,设计了以8*8块处理单元为基础的、支持不同块尺寸的粗选单元模块处理架构。其中,8*8块处理单元采用64点全并行的方式进行预测和STAD值的计算,且不同块间的预测和STAD计算均以流水的方式进行,使模块的数据吞吐率提高到1.5Gbps。本文在设计上述两种硬件架构的基础上,还使用Vivado-HLS工具对两种硬件架构进行了实现,并解决了实现过程中存在的影响硬件并行化设计的数据依赖性问题。最后,对设计实现的两种硬件架构进行了RTL级的仿真测试。仿真结果显示,本文设计实现的硬件架构能够有效地提高HEVC帧内压缩的效率。
[Abstract]:Video, as an important part of multimedia information, has shown a new trend of ultra-high resolution in recent years. However, the H.264/AVC compression standard based on macroblock is becoming more and more difficult to meet the demand of high-definition and ultra-high-definition video compression. In order to meet the demand of ultra high resolution video compression, ITU and the International Organization for Standardization (ISO) jointly put forward the HEVC video compression standard. The compression efficiency of the standard is nearly twice as high as that of H.264/AVC. However, the improvement of the algorithm also leads to the increase of complexity, which brings a great challenge to the design of real-time encoder. Because FPGA has an incomparable advantage in data processing speed, the hardware design of the algorithm, especially the intra prediction algorithm, has become a hot topic in recent years. In addition, the hardware circuit described by software code can be implemented and verified at RTL level by using the Vivado-HLS tool developed by Xilinx, which is compared with the traditional hardware development based on Verilog/VHDL and other hardware description languages. Using HLS tools can easily optimize the design architecture of the module, which greatly shortens the cycle of hardware design and development, which has gradually become a new way of FPGA development. In this paper, we first introduce the intra prediction algorithm of HEVC. Then according to the characteristics of reference point preprocessing module and rough selection module in intra prediction, the pipeline design of reference point preprocessing module suitable for hardware implementation and parallel architecture: 1) the usability judgment of preprocessing algorithm in HEVC standard software are designed. Assignment and smoothing are serially processed. The clock delay of the module is very large and the throughput is not high. In order to reduce the delay and improve the throughput, a pipeline structure of the preprocessing module is designed. Compared with the serial buffer structure of the standard algorithm, the data throughput is improved by four times. Based on the parallel characteristics of rough selection module, a processing architecture of rough selection unit module with different block sizes is designed, which is based on 8 pieces of processing units. The data throughput of the module is increased to 1.5 Gbps because the data throughput of the module is improved to 1.5Gbps. the prediction and STAD calculation among the different blocks are carried out in the way of pipelining. On the basis of the design of the two kinds of hardware architecture, this paper also uses Vivado-HLS tools to implement the two kinds of hardware architecture, and solves the problem of data dependence which affects the hardware parallelization design in the process of implementation. Finally, the RTL level simulation test is carried out on the two kinds of hardware architecture designed and implemented. Simulation results show that the hardware architecture designed in this paper can effectively improve the efficiency of HEVC intra compression.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN919.81

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