基于FPGA的视频监控系统的研究

发布时间：2018-06-13 05:28

本文选题：视频压缩 + JPEG　；参考：《南京大学》2014年硕士论文

【摘要】：随着社会的不断发展、生活水平的提高、工业自动化不断兴起,人和人、人和公共基础设施之间的突发事件也越来越频繁,并且这些突发事件往往具有毫无征兆、难以预测的特征,在这些问题面前,视频监控变得尤为重要。基于FPGA的处理技术具有性能稳定、开发周期短、配置灵活等特点,因而在本系统中采用FPGA作为视频监控系统的核心处理器件。JPEG图像编解码算法是国际上关于静止图像和灰度图像的第一个国际编码标准,JPEG不仅适用于静止图像的压缩编码,而且也可以用来作为视频图像的压缩标准。本文详细研究了基于FPGA的视频图像处理技术,在此基础上设计出一套系统软硬件平台。硬件部分包括视频采集模块、视频编码模块和网络传输模块、网络接收模块、视频解码模块、视频显示模块。软件部分包括JPEG图像编解码算法和基于LWIP的网络传输协议。由于系统功能比较复杂,对FPGA芯片速度以及内部逻辑资源要求较高,因此采用了XILINX公司的VIRTEX-II PRO系列的XC2VP50的FPGA芯片。本视频监控系统分为输入端与输出端两部分。在输入端,视频图像直接由摄像头产生,经由视频编码模块将其压缩为JPEG格式图像数据。在输出端,压缩图像数据通过视频解码模块解码后通过视频显示模块在终端实现显示。对于输入端与输出端之间的实时数据传输,采用移植在Xilinx FPGA上的嵌入式网络Lwip协议栈,,使用UDP传输形式,从而在输出端得到低延时的原始视频图像数据。
[Abstract]:With the continuous development of society, the improvement of living standards, the rising of industrial automation, the emergencies between people and people, between people and public infrastructure are more and more frequent, and these emergencies often have no warning. In the face of these problems, video surveillance becomes more and more important. The processing technology based on FPGA has the characteristics of stable performance, short development period, flexible configuration, etc. Therefore, using FPGA as the core processing device of video surveillance system. JPEG image coding and decoding algorithm is the first international coding standard for still image and gray image, JPEG is not only suitable for still image compression coding. It can also be used as a compression standard for video images. In this paper, the video image processing technology based on FPGA is studied in detail, and a software and hardware platform is designed. The hardware includes video acquisition module, video coding module and network transmission module, network receiving module, video decoding module and video display module. The software includes JPEG image coding and decoding algorithm and LWIP based network transmission protocol. Because of the complexity of the system function and the high requirement of FPGA chip speed and internal logic resources, the XC2VP50 FPGA chip of XILINX company's VIRTEX-II pro series is adopted. The video monitoring system is divided into two parts: input and output. At the input end, the video image is generated directly by the camera and compressed into JPEG format image data by the video coding module. At the output end, the compressed image data is decoded by the video decoding module and displayed at the terminal through the video display module. For the real-time data transmission between input and output, the embedded network Lwip protocol stack is transplanted on Xilinx FPGA, and UDP is used to transmit the original video image data with low delay at the output end.
【学位授予单位】：南京大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN948.6

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