阵列雷达数字接收机测试系统的设计与实现

发布时间：2018-06-19 00:57

本文选题：阵列雷达数字接收机 + 通用串行接口总线　；参考：《电子科技大学》2014年硕士论文

【摘要】：阵列雷达在国防中的应用无处不在,它的发展对于一个国家的军事实力有着深远的影响。而数字接收机作为阵列雷达中必不可少的一部分,它的性能往往决定了阵列雷达的性能。为了能用一个简单有效的方法实现对阵列雷达数字接收机的性能进行评估,本文设计了一个对A/D变换器的相关指标进行测试的测试系统,从而达到对阵列雷达数字接收机的相关性能进行间接测试的目的。整个测试系统是由硬件和软件两部分构成,硬件系统负责数据的采集、存储以及传输;软件系统负责各种功能的实现,包括硬件检测、硬件自检、配置参数和数据传输。为了满足测试系统的需求,一方面对硬件方案中的主要模块进行了论证,另一方面提出了软件方案的整体架构,同时对硬件与软件之间的交互作了简要的说明。硬件系统需要将ADC过后的差分数据通过SN65LVDS386芯片转换成单端数据输入到FPGA,然后采用两片1M*16bit的SRAM完成对两路ADC数据的缓存,最后将数据通过USB2.0接口上传到计算机中。软件系统分为FPGA逻辑设计和USB程序设计两个部分。在设计完FPGA逻辑的主体框架后,对其中的主要功能模块作了详细说明,涵盖了采集模块、SRAM存储模块、通道选择模块、USB传输模块、自检模块和总体控制模块等逻辑设计。USB程序设计部分又分为固件程序设计和功能程序设计,本文除了阐述了固件程序的每个步骤,还对系统所需的功能函数的流程作了介绍。最后对系统的功能进行了验证,并给出了相应的验证结果,同时在与上级板卡联调测试后给出了测试结果,验证结果显示了系统功能的正确性,而测试结果表明测试系统符合预期期望,完成了对A/D指标的测试。
[Abstract]:Array radar is widely used in national defense, and its development has a profound influence on the military strength of a country. As an indispensable part of array radar, the performance of digital receiver often determines the performance of array radar. In order to evaluate the performance of array radar digital receiver with a simple and effective method, this paper designs a testing system to test the relative indexes of the A / D converter. Thus, the correlation of array radar digital receiver can be indirectly tested. The whole test system is composed of hardware and software, the hardware system is responsible for data acquisition, storage and transmission, and the software system is responsible for the realization of various functions, including hardware detection, hardware self-testing, configuration parameters and data transmission. In order to meet the requirements of the test system, on the one hand, the main modules in the hardware scheme are demonstrated; on the other hand, the overall structure of the software scheme is proposed, and the interaction between hardware and software is briefly explained. The hardware system needs to convert the difference data after ADC into single terminal data input into FPGA through SN65LVDS386 chip, then use two pieces of 1MU 16bit SRAM to cache the two ADC data, and finally upload the data to the computer through USB2.0 interface. The software system is divided into two parts: FPGA logic design and USB program design. After designing the main frame of FPGA logic, the main function modules are described in detail, including the acquisition module, the SRAM storage module, the channel selection module and the USB transmission module. The logic design of self-checking module and total control module. USB program design is divided into firmware program design and function program design. This paper not only describes each step of firmware program, but also introduces the flow of the function required by the system. Finally, the function of the system is verified, and the corresponding verification results are given. At the same time, the test results are given after the test with the higher board card. The verification results show the correctness of the system function. The test results show that the test system meets the expected expectations and completes the test of the A / D index.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.5

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