基于混合架构的视频压缩及可靠传输系统的设计及实现

发布时间：2018-06-24 05:10

本文选题：视频压缩 + FPGA　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：近年来,视频图像采集及传输的应用遍布于人类社会的各个领域。因而,视频压缩技术也受到越来越多学者的关注。为了更好地进行视频压缩,视频压缩标准应运而生。当前应用较广也较成熟的压缩标准为H.264。H.264与之前发布的标准相比,压缩性能上有较大提高,使用也更加灵活,应用范围也更广。H.264标准可以根据不同的应用场景提供不同的档次和相应的编码工具包。在压缩性能提升的同时,压缩标准也变得更加复杂。因此实现编码标准需要先进的硬件及软件的支持。本文在综合考虑后,选用当下应用较广且较实用的FPGA+DSP混合架构来实现视频压缩及可靠传输系统,并对其进行了深入研究,主要的研究成果为:1.对视频压缩算法进行研究。首先对视频压缩标准发展历史及现状进行了介绍;接着介绍了视频压缩的基本知识,指出在目前传输技术和存储条件下进行视频压缩是必要的,同时指出视频可以被压缩,是通过去除视频图像中的时间上和空间上及人眼视觉上的冗余来实现的;之后重点介绍了H.264视频压缩标准的详细框架及使用的关键技术:帧间预测、帧内预测、去块滤波器、变换和量化、熵编码及码率控制等。2.对FPGA+DSP的混合架构进行了研究。首先对应用FPGA进行系统开发的优势及FPGA的器件选型做了研究;接着研究了DSP处理器的特点及DSP器件的选型;最后经过综合考虑选择了基于FPGA+DSP的混合视频架构进行视频压缩传输系统的实现,并确定了FPGA和DSP的选型及各自在视频压缩传输系统中的分工。3.对混合架构的视频压缩传输系统的可用方案进行研究。首先对视频图像可用的预处理方案做了研究,包括针对进入视频压缩传输系统的视频格式的预处理方案,针对视频图像中的亮度和色度信号的可选预处理方案,及针对视频图像的缓存机制可选的方案;接着对FPGA与DSP间协同处理时用到的接口及协议做了研究,包括原始视频的传输、压缩码流的传输以及DSP与FPGA的协同启动;之后对压缩后码流的可靠传输方案进行了研究;最后对解码端系统及可选显示方案进行了研究。4.对混合架构的视频压缩传输系统进行了实现。首先设计出了一个针对特定需求的编码端的方案实现框图,详细说明整个流程及各个模块的功能;最后给出相应的解码端方案实现框图、处理流程及内部设定的部分具体参数,同时给出部分modelsim仿真图。
[Abstract]:In recent years, video image acquisition and transmission are widely used in various fields of human society. As a result, video compression technology has attracted more and more attention of scholars. In order to better carry out video compression, video compression standard came into being. The compression standard H.264.H.264, which is widely used and mature, has better compression performance and is more flexible in use than the standard published before. The H.264 standard can provide different grades and corresponding coding toolkits according to different application scenarios. As compression performance improves, compression standards become more complex. Therefore, the implementation of coding standards needs the support of advanced hardware and software. In this paper, we choose the widely used and practical FPGA DSP hybrid architecture to realize the video compression and reliable transmission system, and do a deep research on it. The main research results are as follows: 1. The video compression algorithm is studied. This paper first introduces the history and present situation of video compression standard, then introduces the basic knowledge of video compression, points out that it is necessary to compress video under the current transmission technology and storage conditions, and points out that video can be compressed. It is realized by removing the redundancy of time, space and human vision in video image, and then introduces the detailed frame of H.264 video compression standard and the key technologies used: interframe prediction, intra prediction, deblocking filter, etc. Transform and quantization, Entropy coding and rate control, etc. The hybrid architecture of FPGA DSP is studied. Firstly, the advantages of using FPGA to develop the system and the device selection of FPGA are studied, then the characteristics of DSP processor and the selection of DSP device are studied. Finally, the hybrid video architecture based on FPGA DSP is selected to implement the video compression transmission system, and the selection of FPGA and DSP and the division of labor between FPGA and DSP are determined. The available scheme of video compression transmission system based on hybrid architecture is studied. Firstly, the available preprocessing schemes for video images are studied, including the preprocessing schemes for the video format entering the video compression transmission system, and the optional preprocessing schemes for the brightness and chrominance signals in the video images. Then, the interface and protocol used in collaborative processing between FPGA and DSP are studied, including the transmission of original video, the transmission of compressed bitstream and the cooperative startup between DSP and FPGA. After that, the reliable transmission scheme of compressed bitstream is studied. Finally, the decoding system and optional display scheme are studied. A hybrid video compression transmission system is implemented. First of all, a scheme implementation block diagram is designed to meet the specific requirements, and the whole flow and the functions of each module are explained in detail. Finally, the corresponding decoding implementation block diagram, processing flow and some specific parameters set inside are given. At the same time, part of the modelsim simulation diagram is given.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81

【参考文献】