基于28纳米工艺的光通信芯片低功耗物理设计

发布时间：2018-06-26 20:51

本文选题：超深亚微米 + 模数转换器　；参考：《电子科技大学》2014年硕士论文

【摘要】：随着工艺的的发展,当今的片上系统芯片不仅要求有最小的面积,最优的性能,还要有最低的功耗。低功耗设计首先要求有较低的功耗值,这样设备使用时间更长,还要求有较好的电压降值来保证电路的性能。随着台积电28纳米工艺的成熟,现功耗结构已经发生了变化,这就要求设计者积极应对这些变化,在设计每个阶段注意细节,挖掘并尝试新方法来最大程度降低功耗。随着工艺的发展,芯片面积和线宽越来越小,功耗密度不断增大,给后端物理设计者带来了极大的挑战。本文首先从物理层次上来分析功耗的结构及产生机理。阐述了伴随工艺的发展,功耗结构比例的变化。在此基础上,对系统级,代码设计级,综合级的低功耗设计方法学进行研究。对于电路级的低功耗设计,即为物理实现阶段采取的低功耗策略。在第三章中,实现了一款基于28纳米工艺光通信芯片的低功耗物理设计。由于工作频率高达2.7GHz,所以功耗和电压降将会是除了性能之外的一个很大的瓶颈。主要讲述的是模数转换器子系统级的物理设计,阐述整个项目物理实现过程,包括布局规划,电源网络规划,标准单元布局,低功耗时钟树设计,时钟树后优化,绕线,静态时序分析,物理验证。主要阐述芯片在各个流程阶段遇到的问题,以及解决方法。最后总结了物理设计中的低功耗策略以及功耗分析结果。通过物理设计,使得高阈值的器件的比例达到85%。漏电功耗降低了35%。电压降也达到最初的预期指标。
[Abstract]:With the development of technology, the on-chip system chips require not only the minimum area, optimal performance, but also the lowest power consumption. Low power design requires a lower power value to ensure the performance of the circuit. It also requires a better voltage drop to ensure the performance of the circuit. With the maturity of TSMC 28 nanotechnology, the current power structure has changed, which requires designers to actively deal with these changes, pay attention to details in each stage of design, mining and try new methods to minimize power consumption. With the development of technology, the chip area and linewidth are becoming smaller and smaller, and the power density is increasing, which brings great challenges to the backend physical designers. Firstly, the structure and mechanism of power consumption are analyzed from the physical level. With the development of technology, the ratio of power consumption structure is changed. On this basis, the system-level, code design-level, integrated-level low-power design methodology is studied. For low power design at circuit level, a low power strategy is adopted for the physical implementation phase. In chapter 3, a low power physical design based on 28 nm optical communication chip is implemented. Because the operating frequency is as high as 2.7 GHz, power consumption and voltage drop will be a major bottleneck in addition to performance. This paper mainly describes the physical design of the analog-to-digital converter sub-system, including layout planning, power network planning, standard cell layout, low-power clock tree design, post-clock tree optimization, winding, and so on. Static timing analysis, physical verification. This paper mainly describes the problems encountered in each stage of the chip process, as well as the solution. Finally, the low power strategy and power analysis results in physical design are summarized. By physical design, the proportion of devices with high threshold reaches 85. Leakage power consumption is reduced by 35. The voltage drop also meets the initial expected target.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN929.1;TN402

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