基于FPGA的北斗接收机基带处理设计与仿真

发布时间：2018-06-30 00:34

本文选题：北斗卫星导航系统 + 基带处理　；参考：《北京交通大学》2014年硕士论文

【摘要】：北斗卫星导航系统的高速发展带动了卫星导航产业的快速发展。北斗接收机是北斗卫星导航系统的用户终端设备,低成本、高性能的接收机是其广泛应用的基础。北斗接收机的设计可以分为三个部分：射频前端、基带处理和定位解算。在这三个部分中,基带处理的性能很大程度上决定了接收机的性能,对基带处理的研究是开发高性能接收机的重要环节。基带处理主要完成卫星信号的捕获和跟踪,目的在于使接收机内部产生的载波信号和伪码信号与射频前端输出的中频信号的载波频率和伪码相位保持一致。当跟踪进入稳定状态后,可以解调出卫星的星历和历书数据,提取伪距观测量和多普勒频移值,用于定位解算部分进行PVT(位置、速度和时间)的计算。本文对基于FPGA的北斗接收机实现进行了研究,重点研究了基带处理的捕获和跟踪。北斗卫星信号的捕获是卫星编号、载波频率和伪码相位的三维搜索。常用的信号捕获方法有基于时域的串行滑动相关捕获法、并行频率搜索捕获法、并行码相位搜索捕获法。论文对三种不同捕获算法的计算复杂度及捕获时间进行了对比分析,并选择基于时域的串行滑动相关捕获法的方法设计了BD2的卫星信号捕获。卫星信号的跟踪分为载波跟踪和伪码跟踪。现有跟踪方法实现中,载波跟踪通常采用COSTAS环结构,伪码跟踪多采用延迟锁定环结构。本文也采用了相同的结构对BD2的载波跟踪和码跟踪部分进行了设计。基带处理部分的设计,在基于Xilinx的FPGA+ARM9的硬件平台上进行了初步验证。利用VHDL语言设计了基带相关器的核心模块,如载波NCO模块,码发生器模块和码NCO模块等,并用Modelsim对相关的模块设计进行了仿真。仿真结果表明了设计的正确性。
[Abstract]:The rapid development of Beidou satellite navigation system drives the rapid development of satellite navigation industry. Beidou receiver is the terminal equipment of Beidou satellite navigation system. The low cost and high performance receiver is the basis of its wide application. The design of Beidou receiver can be divided into three parts: RF front end, baseband processing and positioning solution. In these three parts, the performance of baseband processing determines the performance of the receiver to a large extent, and the research of baseband processing is an important part in the development of high performance receiver. The baseband processing mainly accomplishes the acquisition and tracking of satellite signals, the purpose of which is to keep the carrier frequency and pseudo-code phase of the carrier signals and pseudo-code signals generated in the receiver consistent with those of the RF front-end output intermediate frequency signals. After tracking into a stable state, the satellite ephemeris and ephemeris data can be extracted, and pseudo-range observations and Doppler frequency shifts can be extracted, which can be used to calculate the PVT (position, velocity and time) in the location solution. In this paper, the implementation of the Beidou receiver based on FPGA is studied, especially the acquisition and tracking of baseband processing. The acquisition of Beidou satellite signal is a three-dimensional search of satellite number, carrier frequency and pseudo-code phase. The commonly used signal acquisition methods include serial sliding correlation acquisition based on time domain, parallel frequency search acquisition and parallel code phase search acquisition. In this paper, the computational complexity and acquisition time of three different acquisition algorithms are compared and analyzed, and the method of serial sliding correlation acquisition based on time domain is selected to design BD2 satellite signal acquisition. Satellite signal tracking is divided into carrier tracking and pseudo code tracking. In the current implementation of tracking methods, Costas loop is usually used for carrier tracking, and delay locking loop is used for pseudo code tracking. The carrier tracking and code tracking part of BD2 is designed with the same structure. The design of baseband processing is preliminarily verified on the hardware platform of FPGA ARM9 based on Xilinx. The core modules of baseband correlator, such as carrier NCO module, code generator module and code NCO module, are designed by using VHDL language, and the related modules are simulated with Modelsim. The simulation results show that the design is correct.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN96.1

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