一种多模式Turbo译码器IP核的设计与实现

发布时间：2018-07-04 16:01

本文选题：Turbo译码器 + Lookup-Log-MAP算法　；参考：《国防科学技术大学》2014年硕士论文

【摘要】：自Turbo码诞生以来,就以接近香农极限的优异性能得到了通信领域的广泛关注和深入研究。随着长期演进项目的继续推进以及4G时代的到来,对信息传输的可靠性和有效性提出更高的要求,作为无线通信信道编码标准之一的Turbo码更成为研究的热点。本文在深入研究Turbo码理论的基础上,设计了一款旨在提高吞吐率和译码效率的多模式Turbo译码器IP核。本文采用自顶向下的设计方法,完成了Turbo译码器IP核的设计和验证工作,然后进行了性能分析。论文的主要研究内容有:1、基于MATLAB的平台对Lookup-Log-MAP算法进行性能仿真,确定该算法为本设计中采用的译码算法。2、全面设计和实现了支持3G通信协议的多模式Turbo译码器IP核。该IP核采用标准化的接口设计,包括基于AXI协议的数据接口设计,具有更大的带宽、更高的灵活性;基于APB协议的配置总线接口设计,具有更高的稳定性和有效性。3、为提高译码效率、减少延时,该IP核采用四个SISO模块并行译码的结构;每个SISO译码模块采用改进的滑窗算法调度,支持可配置个数范围内的任意情况,提高了设备的可扩展性;通过使用两个单端口存储器进行“乒乓”操作的方式存储前向量度值,减少了控制逻辑,降低了硬件实现复杂度,存储器容量相对于未采用滑窗算法时减小了3/5;设计了基于外信息统计特性的提前停止译码准则,在不降低译码性能的基础上有效减少译码延时。4、该IP核在存储模块和译码模块间增加缓冲模块的设计,解决了存储单元向译码单元供数不足的问题,防止访问冲突的发生。5、经过全面的验证和测试,该IP核功能正确,在65nm CMOS工艺下综合得出其实际工作频率可达到400MHz,误码率和译码速率均达到了多模式Turbo译码器IP核的设计需求。
[Abstract]:Since Turbo code was born, it has received extensive attention and in-depth research in the field of communication for its excellent performance near Shannon limit. With the development of the long-term evolution project and the arrival of 4G era, the reliability and efficiency of information transmission are required higher. As one of the wireless communication channel coding standards, Turbo code has become a hot research topic. Based on the research of Turbo code theory, a multi-mode Turbo decoder IP core is designed to improve throughput and decoding efficiency. In this paper, the design and verification of the IP core of Turbo decoder are completed by using the top-down design method, and then the performance analysis is carried out. The main research contents of this paper are as follows: 1. The performance simulation of Lookup-Log-MAP algorithm based on MATLAB is carried out. It is determined that this algorithm is the decoding algorithm used in this design. The IP core of multi-mode Turbo decoder supporting 3G communication protocol is designed and implemented in an all-round way. The IP core adopts standardized interface design, including data interface design based on AXI protocol, which has higher bandwidth and flexibility, and configuration bus interface design based on APB protocol. In order to improve the decoding efficiency and reduce the delay, the IP core adopts four SISO modules to decode in parallel, each SISO decoding module uses an improved sliding window algorithm. It supports any situation in the range of configurable number, improves the expansibility of the device, stores the forward metric value by using two single-port memory to perform "ping-pong" operation, reduces the control logic and reduces the complexity of hardware implementation. The memory capacity is reduced by 3 / 5 compared with that without the sliding window algorithm, and an early stop decoding criterion based on the statistical characteristics of external information is designed. On the basis of not reducing the decoding performance, the decoding delay. 4 is effectively reduced. The IP core adds buffer modules between the storage module and the decoding module, which solves the problem of the insufficient supply of memory cells to the decoding units. After full verification and test, the IP core has the correct function. The actual working frequency of the IP core can reach 400 MHz in 65nm CMOS technology. The bit error rate and decoding rate are both up to the design requirements of the IP core of the multi-mode turbo decoder.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22

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