EOSVI-CFAR算法研究及硬件设计与实现

发布时间：2018-07-05 15:23

本文选题：VI-CFAR + EOSVI-CFAR　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：雷达信号处理中恒虚警率(CFAR)处理的目的是为了在目标检测过程中可以保证稳定的虚警率。不同的恒虚警率算法在某些环境中有较好的检测性能,但是在其余环境下性能恶化验证。对多种CFAR算法研究后发现,VI-CFAR在均匀背景,杂波边缘背景下均有较好的性能,但在多目标尤其是前后参考窗均存在干扰时其检测性能下降严重。基于这种情况,本文首先提出了一种改进的VI-CFAR检测方法-EOSVI-CFAR,此方法通过改变VI选择不同恒虚警的判别条件并且引入了有序统计OS-CFAR算法。对EOSVI-CFAR进行Matlab建模后,仿真结果表明,改进后的算法有效改善了VI-CFAR的多目标环境下检测性能下降的问题,同时在均匀环境,杂波边缘环境下仍保持着较好的性能。随后本文进行算法的硬件设计。根据要求给出了电路的实现方案,核心的模块包括:累加求和模块、乘累加模块、关键判别函数模块、控制模块、阈值生成模块、高速插入排序模块。为了提高处理器的工作频率,在原有的排序电路基础上提出了新的实现方案,使用ISE Virtex5综合后最大时钟频率比原版提高了10%,大大增强了处理器的性能。对于排序,累加和,乘累加和结果使用延迟电路有效的减小了面积消耗。在功能验证阶段,使用MATLAB,Modelsim联合仿真,将前者的输出结果与后者的输出结果进行对比分析,结果一致证明硬件实现正确。使用DC#174;在0.18μm工艺下综合,面积为760106μm2,最坏情况下时钟频率可达215MHz。第一个数据从输入到结果输出需要31个时钟周期。对RTL和综合的网表做形式验证,结果表明二者一致。最后采用ICC#174;进行后端实现。最终布局布线后核的面积为1520233μm2,功耗为67.8mW。
[Abstract]:The purpose of constant false alarm rate (CFAR) processing in radar signal processing is to ensure a stable false alarm rate in the process of target detection. Different CFAR algorithms have better detection performance in some environments, but in others, the performance deterioration is verified. After studying various CFAR algorithms, it is found that VI-CFAR has better performance in homogeneous background and clutter edge background, but the detection performance of VI-CFAR is degraded seriously when there is interference in multiple targets, especially in front and rear reference windows. Based on this situation, an improved VI-CFAR detection method-EOSVI-CFAR is proposed in this paper. By changing VI to select different CFAR criteria, an ordered statistical OS-CFAR algorithm is introduced. After modeling EOSVI-CFAR with Matlab, the simulation results show that the improved algorithm can effectively improve the performance degradation of VI-CFAR in multi-target environment, while maintaining good performance in homogeneous environment and clutter edge environment. Then this paper designs the hardware of the algorithm. According to the requirements, the implementation scheme of the circuit is given. The core modules include: cumulative summation module, multiplicative accumulation module, key discriminant function module, control module, threshold generation module, high speed insertion sorting module. In order to improve the working frequency of the processor, a new scheme is proposed on the basis of the original sort circuit. The maximum clock frequency of ISE Virtex5 synthesis is 10 times higher than that of the original, which greatly enhances the performance of the processor. For sorting, summation, multiplicative summation and results, delay circuits are used to effectively reduce area consumption. In the phase of function verification, the output results of the former are compared with those of the latter by MATLAB Modelsim simulation. The results show that the hardware implementation is correct. DC#174was used in the process of 0.18 渭 m, the area was 760106 渭 m ~ 2, and the clock frequency could reach 215 MHz in the worst case. The first data requires 31 clock cycles from input to output. The results of formal verification of RTL and synthetic network table show that the two are consistent. Finally, ICC #174 is used to implement the back end. The area of the core is 1520233 渭 m ~ 2 and the power consumption is 67.8 MW.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.51

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