一种线性组合型FRFT的电路实现
发布时间：2018-07-30 08:39
【摘要】：近年来,数字信号处理技术得到了迅速的发展。在数字信号处理领域,传统的傅里叶变换已经发展得比较成熟。但随着应用信号种类的不断扩展,傅里叶变换逐渐显露出其在处理非平稳信号时的局限性。为了解决上述缺陷,小波变换、Gabor变换、Wigner分布以及分数阶傅里叶变换等新的信号分析理论相继问世。分数阶傅里叶变换作为傅里叶变换的广义形式,因其能够很好地表达信号的时频局部特性而受到众多研究者的青睐。本文对分数阶傅里叶变换的离散算法进行了研究与分析,并以FPGA为硬件平台对其中的一种算法进行了电路的设计与实现。本文首先对分数阶傅里叶变换的定义和性质进行了简要的概述,然后分析和对比几种不同的离散算法并阐述了它们各自的优缺点,最后选择了线性组合型的离散算法作为研究对象。此算法继承了连续分数阶傅里叶变换的大部分性质,易于工程实现。线性组合型的离散算法有两种实现方式,即串行方法实现和并行方法实现。本文对比了这两种实现方式。并行实现方式所需要的物理资源是难以承受的,串行实现方法却具有规则的计算结构,适合于VLSI实现。因此,本文将以串行实现方式来设计该离散算法的电路结构。通过对相关理论的分析,本文给出了线性组合型的离散算法的电路设计思路。本文提出的电路结构一共分成四个模块:(1)CORDIC模块;(2)奇数点IFFT模块;(3)矩阵向量乘模块;(4)逻辑控制模块。本文在CORDIC模块中使用Baker预测降低了电路资源消耗,在奇数点IFFT模块中充分利用Winograd算法减少了乘法的次数,在矩阵向量乘模块中通过数据重新排序技术提高了流水线电路的计算效率。本文设计的电路拥有三种工作模式,并且可以很容易地扩展到其它的分数阶信号变换。该电路结构在FPGA上实现所得的结果经测试精度高,最高工作频率可达291MHz。
[Abstract]:In recent years, digital signal processing technology has been rapidly developed. In the field of digital signal processing, the traditional Fourier transform has been more mature. However, with the continuous expansion of the types of applied signals, Fourier transform gradually reveals its limitations in the processing of non-stationary signals. In order to solve the above problems, new signal analysis theories such as wavelet transform Gabor transform Wigner distribution and fractional Fourier transform have been developed one after another. As a generalized form of Fourier transform, fractional Fourier transform (FRT) is favored by many researchers for its ability to express the time-frequency local characteristics of signals. In this paper, the discrete algorithm of fractional Fourier transform is studied and analyzed, and one of the algorithms is designed and implemented using FPGA as the hardware platform. In this paper, the definition and properties of fractional Fourier transform are briefly summarized, then several discrete algorithms are analyzed and compared, and their respective advantages and disadvantages are described. Finally, the linear combinatorial discrete algorithm is chosen as the research object. This algorithm inherits most of the properties of continuous fractional Fourier transform and is easy to be implemented in engineering. There are two ways to realize linear combinatorial discrete algorithm: serial method and parallel method. This paper compares these two methods of implementation. The physical resources required for parallel implementation are unbearable, but the serial implementation method has a regular computing structure, which is suitable for VLSI implementation. Therefore, this paper designs the circuit structure of the discrete algorithm by serial implementation. Based on the analysis of relevant theories, the circuit design idea of linear combinatorial discrete algorithm is given in this paper. The proposed circuit structure is divided into four modules: (1) CORDIC module; (2) odd point IFFT module; (3) matrix vector multiplication module; (4) logic control module. In this paper, Baker prediction is used in CORDIC module to reduce circuit resource consumption, and Winograd algorithm is fully used in odd-point IFFT module to reduce the times of multiplication. The efficiency of pipeline circuit is improved by data reordering in matrix vector multiplication module. The circuit designed in this paper has three working modes and can be easily extended to other fractional signal transformations. The result of the circuit structure realized on FPGA has high precision and the highest working frequency can reach 291 MHz.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.72
本文编号：2154441
[Abstract]:In recent years, digital signal processing technology has been rapidly developed. In the field of digital signal processing, the traditional Fourier transform has been more mature. However, with the continuous expansion of the types of applied signals, Fourier transform gradually reveals its limitations in the processing of non-stationary signals. In order to solve the above problems, new signal analysis theories such as wavelet transform Gabor transform Wigner distribution and fractional Fourier transform have been developed one after another. As a generalized form of Fourier transform, fractional Fourier transform (FRT) is favored by many researchers for its ability to express the time-frequency local characteristics of signals. In this paper, the discrete algorithm of fractional Fourier transform is studied and analyzed, and one of the algorithms is designed and implemented using FPGA as the hardware platform. In this paper, the definition and properties of fractional Fourier transform are briefly summarized, then several discrete algorithms are analyzed and compared, and their respective advantages and disadvantages are described. Finally, the linear combinatorial discrete algorithm is chosen as the research object. This algorithm inherits most of the properties of continuous fractional Fourier transform and is easy to be implemented in engineering. There are two ways to realize linear combinatorial discrete algorithm: serial method and parallel method. This paper compares these two methods of implementation. The physical resources required for parallel implementation are unbearable, but the serial implementation method has a regular computing structure, which is suitable for VLSI implementation. Therefore, this paper designs the circuit structure of the discrete algorithm by serial implementation. Based on the analysis of relevant theories, the circuit design idea of linear combinatorial discrete algorithm is given in this paper. The proposed circuit structure is divided into four modules: (1) CORDIC module; (2) odd point IFFT module; (3) matrix vector multiplication module; (4) logic control module. In this paper, Baker prediction is used in CORDIC module to reduce circuit resource consumption, and Winograd algorithm is fully used in odd-point IFFT module to reduce the times of multiplication. The efficiency of pipeline circuit is improved by data reordering in matrix vector multiplication module. The circuit designed in this paper has three working modes and can be easily extended to other fractional signal transformations. The result of the circuit structure realized on FPGA has high precision and the highest working frequency can reach 291 MHz.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.72
【参考文献】
相关期刊论文 前1条
1 刘沛华;鲁华祥;龚国良;刘文鹏;;基于FPGA的全流水双精度浮点矩阵乘法器设计[J];智能系统学报;2012年04期
，本文编号：2154441
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