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CMOS多通道接收机通道间耦合问题及关键模块研究

发布时间:2018-08-26 15:13
【摘要】:随着无线技术的发展,各种新技术层出不穷,近年来多通道技术的应用极大地提高了无线系统的性能。典型的多通道系统包括有源相控阵系统、MIMO(多输入多输出)系统、阵列成像系统等,相对传统的单通道系统性能得到很大的提升;但是采用传统分立器件搭建的多通道系统也存在成本高、体积大、功耗高和通道间一致性差等缺点。利用高集成度的硅工艺设计多通道芯片是多通道系统发展的必然趋势,然而多个通道集成在同一个衬底,会加剧通道间的耦合,影响了多通道系统的性能。本论文主要研究多通道芯片中通道间的耦合和各模块的设计,所以对多通道系统的发展具有重要意义。本论文的主要工作包括: 一、以焦平面被动成像系统为例,研究通道间耦合对阵列成像系统的影响,这是本文的一个创新点。在传统理论的基础上,建立了被动阵列成像的模型,从理论上推导并证明了通道间耦合对被动阵列成像的影响。 二、分析了几种主要的耦合方式和影响通道间耦合的主要因素,,根据分析的结果针对邻近电感对LNA(低噪声放大器)间耦合的影响建立了模型,并推导出理论结果,这是本文的一个创新点。为了验证理论的正确性,本文采用集成电路仿真软件cadence+电磁场仿真软件sonnet协同仿真的方法与理论结果做对比。最后,在理论结果的指导下利用0.18μm RF CMOS工艺设计制作了四通道接收机,并对比了实测结果与理论结果。 三、以理论分析为指导,提出了2GHz四通道接收芯片的结构;接着在研究LNA的噪声、输入匹配和增益的基础上,提出了LNA的设计流程,并给出了仿真和测试结果;然后研究了MIXER(混频器)的拓扑结构和设计流程,给出了仿真和测试结果;最后给出了2GHz四通道接收芯片的仿真和测试结果。 四、针对参考杂散和锁定时间的矛盾,在传统带宽切换的基础上提出了一种低杂散、快锁定的混合型PLL(锁相环)频率综合器。混合型PLL在瞬态为传统单路径、大环路带宽PLL,在稳态为双路径、小环路带宽PLL,这是本文的一个创新点。最后为了验证理论的正确性,采用0.18μm RF CMOS工艺实现了混合型PLL频率综合器,并给出了PLL的测试结果。
[Abstract]:With the development of wireless technology, a variety of new technologies emerge in endlessly. In recent years, the application of multi-channel technology has greatly improved the performance of wireless systems. Typical multi-channel systems include active phased array systems (MIMO), array imaging systems, and so on. Compared with traditional single-channel systems, the performance of multi-channel systems has been greatly improved. However, the multi-channel system with traditional discrete devices also has the disadvantages of high cost, large volume, high power consumption and poor consistency between channels. It is an inevitable trend for multi-channel systems to design multi-channel chips using highly integrated silicon technology. However, if multiple channels are integrated on the same substrate, the coupling between channels will be aggravated and the performance of multi-channel systems will be affected. This paper mainly studies the coupling between channels and the design of each module in multi-channel chip, so it is of great significance to the development of multi-channel system. The main work of this thesis is as follows: first, the influence of coupling between channels on array imaging system is studied, which is an innovative point of this paper, taking focal plane passive imaging system as an example. Based on the traditional theory, the model of passive array imaging is established, and the influence of coupling between channels on passive array imaging is deduced and proved theoretically. Secondly, several main coupling modes and main factors affecting the coupling between channels are analyzed. According to the analysis results, the influence of adjacent inductors on the coupling between LNA (low noise Amplifier) is modeled, and the theoretical results are derived. This is an innovation of this paper. In order to verify the correctness of the theory, the integrated circuit simulation software cadence electromagnetic field simulation software sonnet collaborative simulation method is used to compare with the theoretical results. Finally, under the guidance of theoretical results, a four-channel receiver is designed and fabricated by using 0.18 渭 m RF CMOS process, and the measured results are compared with the theoretical results. Thirdly, under the guidance of theoretical analysis, the structure of 2GHz four-channel receiving chip is put forward, and the design flow of LNA is put forward on the basis of studying the noise, input matching and gain of LNA, and the simulation and test results are given. Then, the topology and design flow of MIXER are studied, and the simulation and test results are given. Finally, the simulation and test results of 2GHz four-channel receiver are given. 4. In view of the contradiction between reference spurious and locking time, a low spurious and fast locking hybrid PLL frequency synthesizer is proposed based on the traditional bandwidth switching. The hybrid PLL is a traditional single path in transient, the large loop bandwidth PLL, is a double path in steady state, and the small loop bandwidth PLL, is an innovation point in this paper. Finally, in order to verify the correctness of the theory, the hybrid PLL frequency synthesizer is realized by using 0.18 渭 m RF CMOS process, and the test results of PLL are given.
【学位授予单位】:北京理工大学
【学位级别】:博士
【学位授予年份】:2014
【分类号】:TN851

【参考文献】

相关期刊论文 前1条

1 黄进芳;刘荣宜;赖文政;石钧纬;许剑铭;;Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable G_m-C loop filter[J];Chinese Physics B;2012年08期



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