MELP基音检测算法FPGA实现研究
发布时间：2018-08-30 08:33
【摘要】：低速率语音编码技术一直是语音通信领域的一个重要发展方向和研究热点。混合激励线性预测编码(Mixed Excitation Linear Prediction,MELP)算法已被用作美国联邦政府的标准算法,并且成为目前应用在各种通信系统中的许多低速率乃至极低速率语音编码算法的主要参考算法,因此在低速率语音编码领域占有重要的地位。在实际应用中,一种合适的实现平台对MELP算法的有效应用有着重要的影响。目前,研究者一般都以各种DSP处理器为平台对MELP算法的实现进行研究。近年来,随着制造工艺水平的快速发展,现场可编程门阵列(Field Programmable Gate Array,FPGA)芯片的规模已发展到等效于千万级的ASIC门,为其广泛应用于数字信号处理领域创造了条件。随着FPGA在数字信号处理领域中的应用越来越多,基于FPGA平台的语音通信系统的研究也成为实际应用的需要。MELP编码算法中,基音周期是需要计算并编码传输的语音信号的关键特征参数,对算法合成语音的质量有着直接的影响。MELP基音检测算法的作用是提取出语音信号的基音周期,是整个算法中的重要组成部分。MELP基音检测算法的算法复杂度较高,因而很难在FPGA平台上实现。但由于其在语音编码算法中的重要性,本文仍将MELP基音检测算法作为研究对象,对其在FPGA平台上的实现进行了研究。首先,作为理论基础,本文对MELP算法的编解码流程进行了简要介绍,并对MELP基音检测算法的实现过程进行了详细的分析。然后,为在FPGA平台上实现MELP基音检测算法,本文对FPGA及其设计方法进行了研究。最后,本文在MELP基音检测算法的C定点实现程序和对算法原理的理解的基础上,用Verilog HDL设计了MELP基音检测算法的硬件模型,完成了MELP基音检测算法在FPGA平台上的实现。在用Verilog HDL对MELP基音检测算法进行建模时,本文采用了自下而上的设计方法。从最低层的加法、乘法等基本运算单元开始,到整数基音周期计算、分数基音周期计算等高层功能模块,分别建立了相应的硬件模型。通过层层建模最终完成了MELP基音检测算法整体的FPGA实现。并在实现过程中从处理速度和资源消耗两个方面分别对各层模型的设计进行了优化。在对本文的实现结果进行性能分析时,本文通过与Vivado HLS转换相应C语言函数得到的FPGA实现结果相比,结果显示本文实现结果具有良好的面积性能;通过对本文实现的处理时间和计算结果的分析,结果表明本文的实现结果在处理速度和计算结果两个方面也表现良好。
[Abstract]:Low-rate speech coding technology has been an important development direction and research hotspot in the field of speech communication. Hybrid excited Linear Predictive coding (Mixed Excitation Linear Prediction,MELP) algorithm has been used as the standard algorithm of the Federal Government of the United States, and has become the main reference algorithm for many low rate and even very low rate speech coding algorithms used in various communication systems. Therefore, it plays an important role in the field of low rate speech coding. In practical applications, a suitable implementation platform has an important impact on the effective application of MELP algorithm. At present, researchers generally study the implementation of MELP algorithm based on various DSP processors. In recent years, with the rapid development of manufacturing technology, the scale of field programmable gate array (Field Programmable Gate Array,FPGA) chip has developed to equivalent to tens of millions of ASIC gates, which has created conditions for its wide application in the field of digital signal processing. With more and more applications of FPGA in the field of digital signal processing, the research of voice communication system based on FPGA platform has become the need of practical application. Pitch period is the key characteristic parameter of speech signal which needs to be calculated and encoded and transmitted. It has a direct influence on the quality of synthesized speech. The function of MELP pitch detection algorithm is to extract pitch period of speech signal. MELP pitch detection algorithm is an important part of the whole algorithm. The algorithm complexity of MELP pitch detection algorithm is high, so it is difficult to implement on FPGA platform. However, due to its importance in speech coding algorithm, this paper still takes the MELP pitch detection algorithm as the research object, and studies its implementation on the FPGA platform. Firstly, as the theoretical basis, this paper briefly introduces the coding and decoding flow of MELP algorithm, and analyzes the realization process of MELP pitch detection algorithm in detail. Then, in order to realize MELP pitch detection algorithm on FPGA platform, this paper studies FPGA and its design method. Finally, on the basis of the C point realization program of MELP pitch detection algorithm and the understanding of the principle of the algorithm, the hardware model of MELP pitch detection algorithm is designed with Verilog HDL, and the realization of MELP pitch detection algorithm on FPGA platform is completed. In the modeling of MELP pitch detection algorithm with Verilog HDL, the bottom-up design method is adopted in this paper. Starting from the basic operation units of the lowest layer, such as addition and multiplication, to the higher functional modules, such as integer pitch cycle calculation and fractional pitch period calculation, the corresponding hardware models are established respectively. Finally, the whole FPGA implementation of MELP pitch detection algorithm is completed by layer modeling. In the process of implementation, the design of each layer model is optimized from two aspects: processing speed and resource consumption. In the performance analysis of the implementation results of this paper, compared with the FPGA implementation results obtained from the corresponding C language functions converted by Vivado HLS, the results show that the results of this paper have good area performance. Through the analysis of the processing time and the calculation results, the results show that the results of this paper are also good in two aspects: the processing speed and the calculation results.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN912.3
本文编号：2212544
[Abstract]:Low-rate speech coding technology has been an important development direction and research hotspot in the field of speech communication. Hybrid excited Linear Predictive coding (Mixed Excitation Linear Prediction,MELP) algorithm has been used as the standard algorithm of the Federal Government of the United States, and has become the main reference algorithm for many low rate and even very low rate speech coding algorithms used in various communication systems. Therefore, it plays an important role in the field of low rate speech coding. In practical applications, a suitable implementation platform has an important impact on the effective application of MELP algorithm. At present, researchers generally study the implementation of MELP algorithm based on various DSP processors. In recent years, with the rapid development of manufacturing technology, the scale of field programmable gate array (Field Programmable Gate Array,FPGA) chip has developed to equivalent to tens of millions of ASIC gates, which has created conditions for its wide application in the field of digital signal processing. With more and more applications of FPGA in the field of digital signal processing, the research of voice communication system based on FPGA platform has become the need of practical application. Pitch period is the key characteristic parameter of speech signal which needs to be calculated and encoded and transmitted. It has a direct influence on the quality of synthesized speech. The function of MELP pitch detection algorithm is to extract pitch period of speech signal. MELP pitch detection algorithm is an important part of the whole algorithm. The algorithm complexity of MELP pitch detection algorithm is high, so it is difficult to implement on FPGA platform. However, due to its importance in speech coding algorithm, this paper still takes the MELP pitch detection algorithm as the research object, and studies its implementation on the FPGA platform. Firstly, as the theoretical basis, this paper briefly introduces the coding and decoding flow of MELP algorithm, and analyzes the realization process of MELP pitch detection algorithm in detail. Then, in order to realize MELP pitch detection algorithm on FPGA platform, this paper studies FPGA and its design method. Finally, on the basis of the C point realization program of MELP pitch detection algorithm and the understanding of the principle of the algorithm, the hardware model of MELP pitch detection algorithm is designed with Verilog HDL, and the realization of MELP pitch detection algorithm on FPGA platform is completed. In the modeling of MELP pitch detection algorithm with Verilog HDL, the bottom-up design method is adopted in this paper. Starting from the basic operation units of the lowest layer, such as addition and multiplication, to the higher functional modules, such as integer pitch cycle calculation and fractional pitch period calculation, the corresponding hardware models are established respectively. Finally, the whole FPGA implementation of MELP pitch detection algorithm is completed by layer modeling. In the process of implementation, the design of each layer model is optimized from two aspects: processing speed and resource consumption. In the performance analysis of the implementation results of this paper, compared with the FPGA implementation results obtained from the corresponding C language functions converted by Vivado HLS, the results show that the results of this paper have good area performance. Through the analysis of the processing time and the calculation results, the results show that the results of this paper are also good in two aspects: the processing speed and the calculation results.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN912.3
【参考文献】
相关期刊论文 前1条
1 郭立;王妙锋;刘璐;郁理;李琳;;1.6Kb/s类MELP语音压缩编码器的FPGA实现[J];小型微型计算机系统;2008年08期
，本文编号：2212544
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