数字延迟锁相环锁定算法研究
发布时间：2018-09-06 18:56
【摘要】：针对现代微处理器和片上系统中时钟分布的要求,本文对现有的数字延迟锁相环的实现种类进行了总结,根据延迟锁相环锁相速度、面积、功耗等因素的平衡,重点对逐次逼近寄存器式延迟锁相环(Successive Approximation Register controlled Delay-Locked Loop,SAR DLL)进行了研究。在可变逐次逼近寄存器式延迟锁相环的基础上进行了改进,提出了移位-可变逐次逼近寄存器式延迟锁相环。本文所做的主要工作如下:1、在可变逐次逼近寄存器式延迟锁相环的逻辑控制模块中增加移位控制模块,即在传统的二元搜索算法执行前,先运行二倍搜索算法,这样就可以将传统逐次逼近寄存器式延迟锁相环中存在的谐波锁定问题避免;2、在移位控制模块的二倍搜索执行完成之后,实现对应有效控制字位数逐次逼近寄存器的二元搜索;3、增加的死锁重启控制模块克服了传统逐次逼近寄存器式延迟锁相环只能锁定一次的缺点。当延迟锁相环第一次进入锁相状态后,由于环境因素影响跳变到失锁状态后,延迟锁相环可以再次重新启动锁相过程,使延迟锁相环再次进入锁相状态。通过对移位-可变逐次逼近寄存器式延迟锁相环进行前端设计与仿真,仿真结果证明了改进思路的正确性。当控制字有效位数为3时,S-VSAR算法最长锁定时间比VSAR算法最长锁定时间减少了11.1%;当控制字有效位数为12时,S-VSAR算法最长锁定时间比VSAR算法最长锁定时间减少了75.9%。
[Abstract]:According to the requirements of clock distribution in modern microprocessor and on-chip system, this paper summarizes the existing types of digital delay PLL, according to the balance of speed, area, power consumption and other factors of DPLL. Emphasis is placed on the study of successive approximation register type delay phase locked loop (Successive Approximation Register controlled Delay-Locked Loop,SAR DLL). On the basis of variable successive approximation register type delay phase-locked loop, a shift variable successive approximation register type delay phase locked loop is proposed. The main work of this paper is as follows: 1. The shift control module is added to the logic control module of variable successive approximation register type delay phase-locked loop, that is, the double search algorithm is run before the traditional binary search algorithm is executed. In this way, the harmonic locking problem in the traditional successive approximation register type delay phase locked loop can be avoided, and after the double search of the shift control module is completed, The binary search of successive approximation register corresponding to the number of word bits is realized. The added deadlock restart control module overcomes the shortcoming that the traditional successive approximation register type delay phase locked loop can only be locked once. After the delay PLL enters the phase locked state for the first time, the delay-locked loop can restart the phase lock process again because of the influence of environmental factors, so that the delay-phase locked loop can enter the phase-locked state again. Through the front-end design and simulation of shift-variable successive approximation register type delay PLL, the simulation results show that the improved idea is correct. When the significant number of control words is 3, the longest locking time of S-VSAR algorithm is 11.1 less than that of VSAR algorithm, and the longest locking time of S-VSAR algorithm is 75.9 less than that of VSAR algorithm when the effective number of control words is 12:00.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8
本文编号：2227220
[Abstract]:According to the requirements of clock distribution in modern microprocessor and on-chip system, this paper summarizes the existing types of digital delay PLL, according to the balance of speed, area, power consumption and other factors of DPLL. Emphasis is placed on the study of successive approximation register type delay phase locked loop (Successive Approximation Register controlled Delay-Locked Loop,SAR DLL). On the basis of variable successive approximation register type delay phase-locked loop, a shift variable successive approximation register type delay phase locked loop is proposed. The main work of this paper is as follows: 1. The shift control module is added to the logic control module of variable successive approximation register type delay phase-locked loop, that is, the double search algorithm is run before the traditional binary search algorithm is executed. In this way, the harmonic locking problem in the traditional successive approximation register type delay phase locked loop can be avoided, and after the double search of the shift control module is completed, The binary search of successive approximation register corresponding to the number of word bits is realized. The added deadlock restart control module overcomes the shortcoming that the traditional successive approximation register type delay phase locked loop can only be locked once. After the delay PLL enters the phase locked state for the first time, the delay-locked loop can restart the phase lock process again because of the influence of environmental factors, so that the delay-phase locked loop can enter the phase-locked state again. Through the front-end design and simulation of shift-variable successive approximation register type delay PLL, the simulation results show that the improved idea is correct. When the significant number of control words is 3, the longest locking time of S-VSAR algorithm is 11.1 less than that of VSAR algorithm, and the longest locking time of S-VSAR algorithm is 75.9 less than that of VSAR algorithm when the effective number of control words is 12:00.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8
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