高速光通信系统接收机模拟前端电路设计

发布时间：2018-09-10 06:34

【摘要】：数据时代的来临对数据存储、处理、传输提出了更高的要求,目前单位存储成本的降低和处理器性能的提高,使得信号传输变成了大数据时代的瓶颈。近些年来,光通信以其优良的性能得到了政府、企业、研究机构的认可,展示出了巨大的潜能和发展势头。当前,高集成度、低功耗、高速光通信接收机已经成为了研究热点。本论文围绕芯片面积、带宽、噪声、功耗等几方面,设计了一款能用于高速光通信接收机中的模拟前端电路。本论文的主要工作如下：第一,介绍了光通信接收机的一般架构,从所传输的随机序列信号入手,研究了重要参数对于随机序列的影响,为后续的设计提供了理论基础。第二,比较了不同的主放大器结构,选择限幅放大器作为本次设计的主放大器,接着介绍了常见的限幅放大器结构,采用级间负反馈结构实现了无电感化设计,大大减小了芯片面积,在此基础上通过零极点模型,对系统稳定性进行了分析。对片上直流失调消除进行了分析推导,针对65nm下直流失调较大的情况,在反馈环路中增加了误差放大器,实现了良好的直流失调消除。电路在TSMC 65nm CMOS工艺下实现流片,芯片面积为0.11mm2。测试结果显示,限幅放大器的差分电压增益为37dB,-3dB带宽为16.5GHz。在高达26.5GHz的频率范围内,Sddll和Sdd22分别小于-16dB和-9dB。除去测试使用的输出驱动电路,整个芯片在1.2V的电源电压下消耗50mA电流。最后,介绍了常见的跨阻放大器结构,比较了每种结构的优缺点,选择了在共栅极电路的基础上增加反馈的结构,并对噪声、带宽、功耗进行了详细分析和优化。仿真结果显示,跨阻放大器的增益为48dB Ω,带宽为28GHz,输入等效积分噪声3.75uA,S11在31.5GHz内小于-10dB。跨阻放大器在1.2V电源电压下消耗10.8mA电流。将跨阻放大器和限幅放大器级联后得到模拟前端电路的-3dB带宽为18.8GHz,增益为88dBΩ。
[Abstract]:The advent of the data age has put forward higher requirements for data storage, processing and transmission. With the reduction of unit storage cost and the improvement of processor performance, signal transmission has become the bottleneck of big data era. In recent years, optical communication has been recognized by the government, enterprises and research institutions for its excellent performance, showing great potential and development momentum. At present, high-integration, low-power, high-speed optical communication receiver has become a research hotspot. This paper designs an analog front-end circuit which can be used in high-speed optical communication receiver around chip area, bandwidth, noise, power consumption and so on. The main work of this thesis is as follows: firstly, the general architecture of optical communication receiver is introduced. The influence of important parameters on the random sequence is studied, which provides a theoretical basis for the subsequent design. Secondly, the different main amplifier structures are compared, the limiting amplifier is selected as the main amplifier, and the common limiting amplifier structure is introduced. The inductance free design is realized by using the interstage negative feedback structure. The chip area is greatly reduced, and the stability of the system is analyzed by using the zero pole model. The elimination of DC offset on chip is analyzed and deduced. In view of the large DC misalignment in 65nm, an error amplifier is added to the feedback loop, and a good DC offset cancellation is realized. The chip area of the circuit is 0.11mm ~ 2. The test results show that the differential voltage gain of the limiting amplifier is 37 dB / 3dB and the bandwidth is 16.5 GHz. In the frequency range up to 26.5GHz, Sddll and Sdd22 are less than -16 dB and -9 dB, respectively. Except for the output drive circuit used in the test, the whole chip consumes 50mA current at 1.2 V power supply voltage. Finally, the common transresistance amplifier structure is introduced, the advantages and disadvantages of each structure are compared, the feedback structure is selected based on the common grid circuit, and the noise, bandwidth and power consumption are analyzed and optimized in detail. The simulation results show that the gain of the transresistance amplifier is 48dB 惟, the bandwidth is 28GHz, and the input equivalent integral noise of 3.75u Agna S11 is less than -10dB in 31.5GHz. The transresistance amplifier consumes 10.8mA current at 1.2 V supply voltage. After cascading the transresistance amplifier and the limiting amplifier, the analogue front-end circuit has a -3dB bandwidth of 18.8 GHz and a gain of 88dB 惟.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN929.1

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