高速串行收发系统关键模块的研究
发布时间：2018-12-09 12:42
【摘要】：高速串行数据传输要求数据信号在传输线上以单比特形式连续传送,而提高单个数据lane传输带宽的方法是尽量提高时钟频率,但是,增大时钟频率会引起严重的码间干扰,高频分量被严重损耗,而且传输数据中长连续的0或1会使信号下一刻反向跳变值不足,传输线路直流平衡性变差,接收端锁定时钟变的更加困难,这都将降低数据传输率。本文主要做了如下工作:1.在对数据流经的发送端、传输线和接收端的各个模块详细分析的基础上,提出了发送端电路设计架构,划分数字电路和模拟电路部分,定义设计整体和各模块的端口信号,性能指标,各采用数字电路和模拟电路设计方法实现。2.针对传输线直流平衡性和时钟相位差问题,采用数字电路半定制设计方法实现了等时同步FIFO、8B/10B编码器和串化器,其中编码过程分解为3B/4B和5B/6B编码,并设置有效数据字符和控制字符选择信号,以及运行不一致性指示信号,有效地打乱传输数据中长连续0或1,为接收端锁定时钟提供足够的信号跃变;3.针对码间干扰问题,设计具有预加重功能的驱动电路,补偿高频分量在传输线上的损耗。在传统LVDS驱动电路基础上,(1)添加并联分流组件,减小总电阻,增大负载电流;(2)添加第二电流源,增加负载电流值;(3)并联两个CML电路,并将其中一个输出延迟一定时间实现加重信号。半定制设计方法实现数字电路部分,采用Verilog HDL描述其功能,用Modelsim做功能仿真,并在130nm CMOS工艺下,DC软件综合映射其门级网表,分析导出的面积、功耗、时序等报告。LVDS和CML驱动电路本设计采用Virtuoso软件在130nm CMOS工艺下,实现电路结构,在Hspice软件模拟仿真达到3.125Gbps传输带宽,通过添加合适的负载电容,调整mos管的宽长比,减小毛刺,达到最优效果。
[Abstract]:High speed serial data transmission requires the data signal to be transmitted continuously in the form of single bit on the transmission line. The method of increasing the transmission bandwidth of single data lane is to increase the clock frequency as far as possible, but increasing the clock frequency will cause serious inter-symbol interference. The high frequency component is seriously lost, and the long and continuous 0 or 1 in the transmission data will make the reverse jump value of the signal at the next moment insufficient, the DC balance of the transmission line will become worse, and the lock clock of the receiver will become more difficult, which will reduce the data transmission rate. The main work of this paper is as follows: 1. On the basis of the detailed analysis of each module of the transmitting end, transmission line and receiving end of the data flow, this paper puts forward the design architecture of the transmitter circuit, divides the digital circuit and the analog circuit, and defines the whole design and the port signal of each module. Performance index, each using digital circuit and analog circuit design method to achieve. 2. In order to solve the problem of DC balance and clock phase difference of transmission line, an isochronous synchronous FIFO,8B/10B encoder and serializer is implemented by using digital circuit semi-custom design method, in which the encoding process is decomposed into 3B/4B and 5B/6B codes. Effective data characters and control character selection signals are set, and inconsistency indication signals are run to effectively disrupt the length of 0 or 1 in the transmitted data, so as to provide sufficient signal jump for the lock clock at the receiving end. 3. To solve the problem of inter-symbol interference (ISI), a driving circuit with preweighting function is designed to compensate the loss of high-frequency components on transmission lines. On the basis of the traditional LVDS drive circuit, (1) adding shunt component to reduce the total resistance and increase the load current, (2) adding the second current source to increase the load current value; (3) parallel two CML circuits, and delay one of them to realize the accentuation signal. The semi-custom design method is used to realize the digital circuit. Verilog HDL is used to describe the function, and Modelsim is used to simulate the function. Under the 130nm CMOS process, the DC software synthetically maps its gate network table, and analyzes the area and power consumption derived. The design of LVDS and CML driver circuit uses Virtuoso software under 130nm CMOS technology to realize the circuit structure, in the Hspice software simulation to achieve 3.125Gbps transmission bandwidth, through the addition of appropriate load capacitance, adjust the mos tube width ratio, Reduce the burr to achieve the best effect.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.3
本文编号：2369380
[Abstract]:High speed serial data transmission requires the data signal to be transmitted continuously in the form of single bit on the transmission line. The method of increasing the transmission bandwidth of single data lane is to increase the clock frequency as far as possible, but increasing the clock frequency will cause serious inter-symbol interference. The high frequency component is seriously lost, and the long and continuous 0 or 1 in the transmission data will make the reverse jump value of the signal at the next moment insufficient, the DC balance of the transmission line will become worse, and the lock clock of the receiver will become more difficult, which will reduce the data transmission rate. The main work of this paper is as follows: 1. On the basis of the detailed analysis of each module of the transmitting end, transmission line and receiving end of the data flow, this paper puts forward the design architecture of the transmitter circuit, divides the digital circuit and the analog circuit, and defines the whole design and the port signal of each module. Performance index, each using digital circuit and analog circuit design method to achieve. 2. In order to solve the problem of DC balance and clock phase difference of transmission line, an isochronous synchronous FIFO,8B/10B encoder and serializer is implemented by using digital circuit semi-custom design method, in which the encoding process is decomposed into 3B/4B and 5B/6B codes. Effective data characters and control character selection signals are set, and inconsistency indication signals are run to effectively disrupt the length of 0 or 1 in the transmitted data, so as to provide sufficient signal jump for the lock clock at the receiving end. 3. To solve the problem of inter-symbol interference (ISI), a driving circuit with preweighting function is designed to compensate the loss of high-frequency components on transmission lines. On the basis of the traditional LVDS drive circuit, (1) adding shunt component to reduce the total resistance and increase the load current, (2) adding the second current source to increase the load current value; (3) parallel two CML circuits, and delay one of them to realize the accentuation signal. The semi-custom design method is used to realize the digital circuit. Verilog HDL is used to describe the function, and Modelsim is used to simulate the function. Under the 130nm CMOS process, the DC software synthetically maps its gate network table, and analyzes the area and power consumption derived. The design of LVDS and CML driver circuit uses Virtuoso software under 130nm CMOS technology to realize the circuit structure, in the Hspice software simulation to achieve 3.125Gbps transmission bandwidth, through the addition of appropriate load capacitance, adjust the mos tube width ratio, Reduce the burr to achieve the best effect.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.3
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