QC-LDPC码的优化设计及其解码器的硬件实现
发布时间：2018-12-11 15:31
【摘要】：低密度奇偶校验(LDPC)码是一种逼近香农极限的信道编码,它是由Gallager在1962年首次提出,然而由于受到当时技术的限制,LDPC码没能得到重视。直到1996年,LDPC码才被编码研究人再次发现,并将其进一步推广。近几年,LDPC码凭借其自身的众多优点,成为第四代移动通信技术(4G)的信道编码方案,再次被人们所关注。近几年,研究LDPC码编解码器硬件实现的学者大量涌现。由于LDPC码校验矩阵结构具有随机性,因此给硬件实现带来很大的困难。准循环低密度奇偶校检(QC-LDPC)码的提出,其独特的准循环特性,降低了编解码的实现复杂度。之后,一些学者和专家基于TPMP算法提出了TDMP类算法,并提出了相应的分层解码算法及其分层解码结构。此解码结构能很好的在硬件消耗和解码性能之间取得平衡,因此成为QC-LDPC解码器的主流结构。本文首先分析了LDPC和QC-LDPC码的相关概念,并重点研究了基于有限域乘群构造无短四环的QC-LDPC码的方法。其次,重点研究了LDPC码的几种常用的软判决解码算法,通过软件仿真确定了归一化最小和算法校正因子的最优解为0.8。通过对各个解码算法的性能比较与详细分析,确定了分层解码算法为最优的硬件实现解码算法。通过软件仿真确定了硬件实现时数据量化比特数为7比特。最后,利用Quartus II 9.0软件,采用Verilog HDL语言,基于自顶向下的模块设计方法,对解码器进行了程序设计,并在Altera公司StratixII系列的EP2S60F484C4器件上,对所设计的解码器进行了布局布线与综合,利用ModelSim 6.4a软件进行了仿真测试,验证了所设计解码器功能的正确性。解码器在最大迭代次数为5,工作时钟频率设为35MHz时,吞吐率已达到92.27Mbps。
[Abstract]:Low-density parity check (LDPC) codes are channel codes that approach the Shannon limit, which was first proposed by Gallager in 1962. However, due to the limitations of technology at that time, LDPC codes have not been paid much attention to. It was not until 1996 that LDPC codes were discovered again by coding researchers and further extended. In recent years, LDPC code has become the channel coding scheme of the fourth generation mobile communication technology (4G) by virtue of its many advantages. In recent years, a large number of scholars have emerged to study the hardware implementation of LDPC codec. Due to the randomness of the LDPC code check matrix structure, it is difficult to implement the hardware. The proposed quasi-cyclic low-density parity check (QC-LDPC) codes have unique quasi-cyclic characteristics and reduce the complexity of coding and decoding. After that, some scholars and experts put forward the TDMP class algorithm based on the TPMP algorithm, and put forward the corresponding layered decoding algorithm and its hierarchical decoding structure. This decoding structure can achieve a good balance between hardware consumption and decoding performance, so it becomes the mainstream structure of QC-LDPC decoder. In this paper, the concepts of LDPC and QC-LDPC codes are analyzed, and the method of constructing QC-LDPC codes without short four rings based on finite field multiplicative groups is studied. Secondly, several commonly used soft decision decoding algorithms for LDPC codes are studied, and the optimal solution of normalized minimum and correction factor is determined to be 0.8 by software simulation. By comparing and analyzing the performance of each decoding algorithm, it is determined that the layered decoding algorithm is the best hardware decoding algorithm. Through the software simulation, the quantization bit number of the hardware is determined to be 7 bits. Finally, using Quartus II 9.0 software and Verilog HDL language, based on the top-down module design method, the decoder is programmed and implemented on the EP2S60F484C4 device of StratixII series of Altera Company. The layout, wiring and synthesis of the designed decoder are carried out, and the correctness of the designed decoder is verified by using ModelSim 6.4a software. When the maximum iteration number is 5 and the working clock frequency is set to 35MHz, the throughput has reached 92.27 Mbps.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22
，
本文编号：2372793
[Abstract]:Low-density parity check (LDPC) codes are channel codes that approach the Shannon limit, which was first proposed by Gallager in 1962. However, due to the limitations of technology at that time, LDPC codes have not been paid much attention to. It was not until 1996 that LDPC codes were discovered again by coding researchers and further extended. In recent years, LDPC code has become the channel coding scheme of the fourth generation mobile communication technology (4G) by virtue of its many advantages. In recent years, a large number of scholars have emerged to study the hardware implementation of LDPC codec. Due to the randomness of the LDPC code check matrix structure, it is difficult to implement the hardware. The proposed quasi-cyclic low-density parity check (QC-LDPC) codes have unique quasi-cyclic characteristics and reduce the complexity of coding and decoding. After that, some scholars and experts put forward the TDMP class algorithm based on the TPMP algorithm, and put forward the corresponding layered decoding algorithm and its hierarchical decoding structure. This decoding structure can achieve a good balance between hardware consumption and decoding performance, so it becomes the mainstream structure of QC-LDPC decoder. In this paper, the concepts of LDPC and QC-LDPC codes are analyzed, and the method of constructing QC-LDPC codes without short four rings based on finite field multiplicative groups is studied. Secondly, several commonly used soft decision decoding algorithms for LDPC codes are studied, and the optimal solution of normalized minimum and correction factor is determined to be 0.8 by software simulation. By comparing and analyzing the performance of each decoding algorithm, it is determined that the layered decoding algorithm is the best hardware decoding algorithm. Through the software simulation, the quantization bit number of the hardware is determined to be 7 bits. Finally, using Quartus II 9.0 software and Verilog HDL language, based on the top-down module design method, the decoder is programmed and implemented on the EP2S60F484C4 device of StratixII series of Altera Company. The layout, wiring and synthesis of the designed decoder are carried out, and the correctness of the designed decoder is verified by using ModelSim 6.4a software. When the maximum iteration number is 5 and the working clock frequency is set to 35MHz, the throughput has reached 92.27 Mbps.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22
，
本文编号：2372793
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