数字下变频及数字波束形成的设计与实现
发布时间：2019-01-07 15:36
【摘要】：雷达信号处理器是雷达系统的关键组成,现代战场上其面对的环境越来越复杂,面对的挑战越来越严峻,对雷达信号处理器的要求不仅是实时性,更要求其具有抗干扰、抗辐射等特性,数字化的阵列雷达信号处理因其具有诸多优秀的特性而成为一种发展的趋势。数字下变频(DDC)将模数转换器(ADC)采样后的数据混频到零频,滤除无用信息,并进行抽取操作,便于后级进行数字信号处理(DSP)。数字波束形成(DBF)能够对阵列天线接收的信息充分利用,通过加权运算,产生特定指向的波束,可以进行抑制干扰、波束扫描等操作。DDC和DBF是数字化阵列雷达信号处理器的关键单元,本文分别对其设计与实现进行了研究,主要工作有:1.根据雷达信号处理器的灵活性要求,运用有限状态机技术设计了可配置DDC。该设计可以实现滤波阶数、滤波系数和抽取倍数的可配置,并运用多通道FIR结构进行时分复用。对该DDC电路进行MATLAB和Modelsim联合仿真,并使用FPGA平台进行原型验证。基于SMIC 0.13μm的标准工艺库完成了逻辑综合、静态时序分析和形式验证,频率可达166MHz,面积为609035μm2。2.根据雷达信号处理器的低成本要求,设计了低成本DDC。将混频、滤波和抽取三个模块合并,提出了多相混频抽取滤波器,并运用多通道FIR结构进行时分复用,减小了面积,降低了成本。对该DDC电路进行MATLAB和Modelsim联合仿真,并使用FPGA平台进行原型验证。基于SMIC 0.13μm的标准工艺库完成了逻辑综合、静态时序分析和形式验证,频率可达166MHz,面积为177533μm2。3.根据雷达信号处理器的高速率要求,设计了高速率DDC。运用多相滤波结构对输入数据划分通道,实现了对高速率输入数据的下变频处理。对该DDC电路进行MATLAB和Modelsim联合仿真,并使用FPGA平台进行原型验证。基于SMIC0.13μm的标准工艺库完成了逻辑综合、静态时序分析和形式验证,频率可达1GHz,面积为376454μm2。4.根据DBF原理,对8阵元DBF进行了MATLAB建模。并运用最小均方差准则、最大信噪比准则和线性约束最小方差准则进行了8阵元自适应数字波束形成(ADBF)的MATLAB建模。对8阵元DBF进行电路设计,基于Virtex 4器件进行功能验证,综合后最高频率为270.53MHz。
[Abstract]:Radar signal processor is the key component of radar system. The environment it faces on the modern battlefield is becoming more and more complex and the challenge is becoming more and more severe. The requirement of radar signal processor is not only real-time, but also anti-jamming. The digital array radar signal processing has become a development trend because of its many excellent characteristics. Digital down conversion (DDC) (DDC) mixes the data sampled by (ADC) to zero frequency, filter out useless information, and decimate, which is convenient for digital signal processing (DSP). Digital beamforming (DBF) can make full use of the information received by the array antenna, and through weighting operation, it can produce a specific direction beam, which can suppress interference. Beam scanning and other operations. DDC and DBF are the key units of digital array radar signal processor. The design and implementation of them are studied in this paper. The main work is as follows: 1. According to the flexibility requirement of radar signal processor, a configurable DDC. is designed using finite state machine technology. This design can realize the configuration of filter order, filter coefficient and decimation multiple, and use multi-channel FIR structure for time division multiplexing. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC 0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 166 MHz and the area is 609035 渭 m 2.2. According to the low cost requirement of radar signal processor, a low cost DDC. is designed. Mixing, filtering and decimating modules are combined, and a multiphase mixing decimation filter is proposed. The multichannel FIR structure is used for time division multiplexing, which reduces the area and cost. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC 0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 166MHz and the area is 177533 渭 m 2.3. According to the high rate requirement of radar signal processor, a high rate DDC. is designed. The input data is divided into channels by using polyphase filter structure, and the downconversion processing of high rate input data is realized. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 1 GHz and the area is 376454 渭 m 2.4. According to the principle of DBF, the 8 matrix DBF is modeled by MATLAB. The MATLAB model of adaptive digital beamforming (ADBF) based on 8-element adaptive digital beamforming is established by using the minimum mean square error criterion, the maximum signal-to-noise ratio criterion and the linear constraint minimum variance criterion. The circuit design of 8 array element DBF is carried out, and the function is verified based on Virtex 4 device. The highest frequency of synthesis is 270.53 MHz.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.51
本文编号：2403827
[Abstract]:Radar signal processor is the key component of radar system. The environment it faces on the modern battlefield is becoming more and more complex and the challenge is becoming more and more severe. The requirement of radar signal processor is not only real-time, but also anti-jamming. The digital array radar signal processing has become a development trend because of its many excellent characteristics. Digital down conversion (DDC) (DDC) mixes the data sampled by (ADC) to zero frequency, filter out useless information, and decimate, which is convenient for digital signal processing (DSP). Digital beamforming (DBF) can make full use of the information received by the array antenna, and through weighting operation, it can produce a specific direction beam, which can suppress interference. Beam scanning and other operations. DDC and DBF are the key units of digital array radar signal processor. The design and implementation of them are studied in this paper. The main work is as follows: 1. According to the flexibility requirement of radar signal processor, a configurable DDC. is designed using finite state machine technology. This design can realize the configuration of filter order, filter coefficient and decimation multiple, and use multi-channel FIR structure for time division multiplexing. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC 0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 166 MHz and the area is 609035 渭 m 2.2. According to the low cost requirement of radar signal processor, a low cost DDC. is designed. Mixing, filtering and decimating modules are combined, and a multiphase mixing decimation filter is proposed. The multichannel FIR structure is used for time division multiplexing, which reduces the area and cost. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC 0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 166MHz and the area is 177533 渭 m 2.3. According to the high rate requirement of radar signal processor, a high rate DDC. is designed. The input data is divided into channels by using polyphase filter structure, and the downconversion processing of high rate input data is realized. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 1 GHz and the area is 376454 渭 m 2.4. According to the principle of DBF, the 8 matrix DBF is modeled by MATLAB. The MATLAB model of adaptive digital beamforming (ADBF) based on 8-element adaptive digital beamforming is established by using the minimum mean square error criterion, the maximum signal-to-noise ratio criterion and the linear constraint minimum variance criterion. The circuit design of 8 array element DBF is carried out, and the function is verified based on Virtex 4 device. The highest frequency of synthesis is 270.53 MHz.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.51
【参考文献】
相关硕士学位论文 前1条
1 倪丁华;分块并行DBF算法及其实现[D];南京理工大学;2009年
，本文编号：2403827
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