基于数字锁相环的低功耗时钟发生器设计

发布时间：2019-02-23 15:55

【摘要】：锁相环的概念自提出之日起,凭借着其优异的特性在电子和通信领域中被广泛应用,比如频率综合器、时钟数据恢复电路。然而,现代多媒体通信市场日新月异,人们对于锁相环的设计提出了更为严格的要求,使得锁相环的设计不断地面临着新的挑战：一方面,对于高频率、多带宽等高性能的锁相环设计要求越来越严格；另一方面,低成本、低功耗也日益成为现代多媒体通信发展所关注的焦点。因此,高性能、低成本和低功耗的锁相环设计成为人们关注的焦点。在这样的大背景下,本论文确立了设计一款用于时钟发生器的全数字锁相环,并且要实现低功耗、全数字化的设计方向。本论文在锁相环的基础之上,讨论了全数字锁相环的设计,包括数控振荡器、数控环路滤波器、数控分频器和鉴相器。重点探讨了数控振荡器的设计,利用CMOS电流域逻辑和MOS变容管技术,设计了一款数控环形振荡器。此外还重点关注了数控环路滤波器的设计,利用经典的积分和比例路径的滤波器结构,实现了数控环路滤波器的设计。针对全数字化的设计方向,本论文设计的全数字锁相环仅由MOS管构成,不包含任何的无源器件,有利于节省芯片面积,降低成本。在低功耗方面,该全数字锁相环利用频率控制字预置技术,加快锁相环的建立,减少锁定时间,以此来降低全数字锁相环工作的平均功耗。本论文采用SMIC013的工艺,设计了一款用于时钟发生器的全数字锁相环,并进行了流片。后仿真结果表明,输出频率范围可以达至(?)92—500MHz,抖动方面在92MHz时约为42.2ps,500MHz时约为9.25ps,功耗方面在92MHz时约为0.33mW,500MHz时约为1.32mW。此外,对芯片进行了测试,给出了更接近真实性能的数据。
[Abstract]:The concept of phase-locked loop (PLL) has been widely used in electronic and communication fields such as frequency synthesizer and clock data recovery circuit since it was proposed. However, the modern multimedia communication market is changing with each passing day, people put forward more stringent requirements for the design of PLL, which makes the design of PLL constantly face new challenges: on the one hand, for high frequency, The design requirements of high performance PLL, such as multi-bandwidth, are becoming more and more stringent. On the other hand, low cost and low power consumption have increasingly become the focus of modern multimedia communication development. Therefore, high performance, low-cost and low-power PLL design has become the focus of attention. In this context, this paper establishes the design direction of a digital phase-locked loop for clock generator, and to achieve low power consumption and digital design. Based on the phase-locked loop, this paper discusses the design of all-digital phase-locked loop, including numerical controlled oscillator, numerical control loop filter, numerical control frequency divider and phase discriminator. The design of numerical controlled oscillator is discussed in detail. A numerical control ring oscillator is designed by using CMOS electric basin logic and MOS varactor technology. In addition, the design of numerical control loop filter is focused on, and the design of numerical control loop filter is realized by using the classical filter structure of integral and proportional path. Aiming at the whole digital design direction, the all-digital phase-locked loop designed in this paper is only composed of MOS tubes and does not contain any passive devices, which is beneficial to saving chip area and reducing cost. In the aspect of low power consumption, this all-digital phase-locked loop uses frequency control word preset technology to speed up the establishment of phase-locked loop and reduce the locking time, thereby reducing the average power consumption of the all-digital phase-locked loop. In this paper, an all-digital phase-locked loop for clock generator is designed by using SMIC013 technology, and the flow sheet is carried out. The simulation results show that the output frequency range can reach 92-500 MHz, the jitter is about 42.2 ps-1 / 500MHz and the power consumption is about 0.33mW / 500MHz and 1.32mW at 92MHz / 500MHz, respectively. The simulation results show that the output frequency can reach 92-500MHz, the jitter is about 42.2 psps / 500MHz, and the power consumption is about 1.32mW when 92MHz is about 0.33mW / 500MHz. In addition, the chip is tested, and the data which is closer to the real performance are given.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

【共引文献】