基于FPGA的32点FFT算法的设计与实现

发布时间：2019-02-24 15:07

【摘要】：数字信号处理技术在当今社会的快速发展,得益于科学技术的快速前进，并且广泛的应用在各种通信和计算机等领域，其中作为数字信号处理的基础运算的离散傅里叶变换DFT在技术的运用中扮演者关键的角色，考虑到效率问题影响了离散傅里叶变换的应用，有人在二十世纪六十年代提出了快速傅里叶变换，也就是FFT，它有效地解决了前者的运算量庞大的问题，，并随着科学技术的进步，它已成为DSP领域的重要技术。 FPGA现场可编程门阵列的出现使得数字信号处理的应用变得更加便捷，它基于PAL、GAL以及CPLD等技术的成熟而出现，它具有更灵活的编辑功能、很多的连接单元，非常适合于短周期的原型设计，相较传统的成批量DSP和ASIC来说，更低的成本及更低的功耗使得人们更倾向选择FPGA来作为开发的工具。这是因为FPGA的构成由硬件完成的，所以FPGA的基本构造较为简单，一般情况下能够包括较多的类似运算模块，如此一来在实现同一功能的条件下，FPGA的处理运算速度会比普通的DSP芯片快很多。由于FFT较为固定的运算结构，由FPGA来实现是非常合适的，同时这种实现方式具备了设计要求的高效性和灵活性。因此，本文选择使用赛灵思Altera的芯片来实现32点的FFT时域抽取的顺序处理器，这是一种通用的可以在FPGA上实现32点FFT变换的方法。整个FFT处理器采用了基-2时域抽取的基本算法原理，与此同时将流水线和并行的设计思想融入了FFT处理器的蝶形运算模块的设计当中，同时处理器包含有地址产生模块、时序控制模块以及存储模块等其它模块,这样便组成了设计所要求的基-2FFT处理器。采用第三方的仿真软件Modelsim对FFT模块的前后设计流程进行了仿真Matlab软件计并与算出精确地算法仿真结果,将它与设计的结果进行对比，验证了该设计的准确性。仿真结果表明，设计的FFT处理器在满足一定精度条件下，能够顺利地通过设计的基本指标。
[Abstract]:The rapid development of digital signal processing technology in today's society, thanks to the rapid progress of science and technology, and widely used in various communications and computer fields, The discrete Fourier transform (DFT), which is the basic operation of digital signal processing, plays a key role in the application of the technology. Considering the efficiency problem, the application of discrete Fourier transform is affected. In the sixties of the 20th century, some people put forward the fast Fourier transform, that is, FFT, which effectively solves the problem that the former has a huge amount of computation, and with the progress of science and technology, it has become an important technology in the field of DSP. The appearance of FPGA field programmable gate array makes the application of digital signal processing more convenient. It is based on the mature technology of PAL,GAL and CPLD. It has more flexible editing function and many connecting units. It is suitable for short period prototype design. Compared with traditional batch DSP and ASIC, lower cost and lower power consumption make people more inclined to choose FPGA as a development tool. This is because the composition of FPGA is made up of hardware, so the basic structure of FPGA is relatively simple. In general, it can include more similar computing modules, so that under the condition of realizing the same function, The processing speed of FPGA is much faster than that of ordinary DSP chips. Because of the fixed operation structure of FFT, it is very suitable to realize it by FPGA, and this implementation method has the high efficiency and flexibility of design requirement at the same time. Therefore, in this paper, we choose to use Altera chip to realize 32-point FFT time-domain decimation sequence processor, which is a universal method to realize 32-point FFT transform on FPGA. The whole FFT processor adopts the basic algorithm of base-2 time domain extraction. At the same time, the pipeline and parallel design ideas are integrated into the design of the butterfly operation module of the FFT processor, and the processor includes the address generation module. Timing control module, storage module and other modules, so as to form the design of the base-2FFT processor. The design flow of FFT module is simulated by the third-party simulation software Modelsim, and the simulation results of the algorithm are calculated and calculated accurately. The accuracy of the design is verified by comparing it with the results of the design. The simulation results show that the designed FFT processor can successfully pass the basic index of the design under certain precision conditions.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN791;TN911.72

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