全数字高速并行QPSK解调技术的研究与实现

发布时间：2019-05-11 01:09

【摘要】：随着空间科学技术的飞速发展和对宇宙空间的不断探索,无线通信数据传输速度逐渐增大,对传输设备的实时性和误码率要求越来越高。目前国内数据传输技术比较落后,并不能达到卫星图像数据高速传输的要求,因此有必要对数据传输系统进行研究。调制解调技术是高速无线通信的核心技术并且也是目前数据传输系统研究的难点。当基带数据速率比较高时,解调端需要处理更加高速的串行数据,如果直接运行解调算法就要求数字芯片有比较丰富的资源和比较高的工作时钟,而当前比较常用数字芯片FPGA内部工作时钟超过400MHz时很容易产生误码,需要对于复杂的解调算法并行处理才能满足高速数据传输的要求。论文主要对全数字高速并行QPSK解调技术的实现进行研究。首先对调制解调原理进行详细分析和推导,其中主要包括数字下变频、载波同步、环路滤波器、数控振荡器、基于横向滤波器的均衡器等。其次通过对基本调制解调算法的推导可得到在解调运算过程中数字下变频和低通滤波器需要处理的数据最多,并且大部分数据采用乘法运算。乘法运算会耗费大量资源并且严重影响解调的速度,为了实现高速解调输出,需要采用并行滤波器来实现数据快速处理。论文中主要介绍了CIC滤波器、时域并行滤波器,分析了两种滤波器的优缺点和适用范围。通过对线性卷积和循环卷积的讨论,提出利用卷积的相关定理和FFT快速算法进行频域并行滤波,其中频域并行滤波一般可采用两种方法实现:以线性卷积为基础的重叠相加法;以循环卷积为基础的重叠保留法。然后通过MATLAB/Simulink平台的对QPSK调制解调基本原理进行建模仿真,利用Simulink工具中示波器、频谱仪、信号源等模块对仿真模型功能验证,得到硬件实现的关键参数。最后编写Verilog硬件并行解调程序对硬件系统实时测试和分析,通过观察信号频谱图、眼图、星座图等表明利用FPGA规模换取处理速度,可以实现高速信号解调输出,并且整个硬件设计比较简单,具有较高的解调性能。综上,通过对高速并行QPSK调制解调等相关原理进行研究和分析,利用MATLAB/Simulink建模与仿真,编写硬件Verilog程序进行在线实时测试和分析,测试结果表明基于FPGA的高速并行解调技术可以达到相关指标要求,大幅度提高了硬件解调速率,对今后进一步研究具有非常重要的意义。
[Abstract]:With the rapid development of space science and technology and the continuous exploration of space, the transmission speed of wireless communication data is increasing gradually, and the real-time performance and bit error rate (BER) of transmission equipment are required more and more. At present, domestic data transmission technology is relatively backward, and can not meet the requirements of high-speed transmission of satellite image data, so it is necessary to study the data transmission system. Modulation and demodulation technology is the core technology of high-speed wireless communication and is also the difficulty of data transmission system research. When the baseband data rate is relatively high, the demodulator needs to deal with more high speed serial data. If the demodulation algorithm is run directly, the digital chip will have more abundant resources and higher working clock. At present, when the internal working clock of FPGA exceeds 400MHz, it is easy to generate error code. It needs parallel processing of complex demodulation algorithm to meet the requirements of high-speed data transmission. In this paper, the implementation of all-digital high-speed parallel QPSK demodulation technology is studied. Firstly, the principle of modulation and demodulation is analyzed and deduced in detail, including digital down conversion, carrier synchronization, loop filter, numerical control oscillator, equalizer based on transversal filter and so on. Secondly, through the derivation of the basic modulation and demodulation algorithm, we can get the most data that digital down conversion and low pass filter need to deal with in the process of demodulation operation, and most of the data use multiplication operation. Multiplication will consume a lot of resources and seriously affect the speed of demodulation. In order to achieve high-speed demodulation output, parallel filter is needed to achieve fast data processing. In this paper, CIC filter and time domain parallel filter are introduced, and the advantages, disadvantages and applicable range of the two filters are analyzed. Based on the discussion of linear convolution and cyclic convolution, the parallel filtering in frequency domain is proposed by using the correlation theorem of convolution and FFT fast algorithm, in which the parallel filtering in frequency domain can be realized by two methods: overlapping addition method based on linear convolution; Overlapping retention method based on cyclic convolution. Then the basic principle of QPSK modulation and demodulation is modeled and simulated by MATLAB/Simulink platform. The function of the simulation model is verified by oscilloscope, spectrometer, signal source and other modules in Simulink tool, and the key parameters of hardware implementation are obtained. Finally, the Verilog hardware parallel demodulation program is compiled to test and analyze the hardware system in real time. By observing the signal spectrum diagram, eye diagram, constellation diagram and so on, it is shown that the high speed signal demodulation output can be realized by using FPGA scale in exchange for processing speed. And the whole hardware design is relatively simple, with high demodulation performance. In summary, through the research and analysis of the related principles of high-speed parallel QPSK modulation and demodulation, using MATLAB/Simulink modeling and simulation, the hardware Verilog program is written for on-line real-time test and analysis. The test results show that the high speed parallel demodulation technology based on FPGA can meet the requirements of the relevant indexes and greatly improve the hardware demodulation rate, which is of great significance for further research in the future.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.3

【共引文献】