MICS接收机中小数分频锁相环的研究与设计
发布时间：2019-05-20 18:03
【摘要】：无线通讯市场的迅速增长,带来了对高性能低成本射频集成电路的迫切需求。同时半导体产业的迅猛发展也为所有通信模块集成在一块芯片上提供了可能。其中,最难集成的便是提供本振信号的锁相环。因为锁相环的相位噪声很难满足无线通信系统的相位噪声需求。因此,对各种锁相环的研究也越来越多。从整数分频到小数分频,从模拟到数字,锁相环的性能不断得到提升,而成本不断降低。频率合成器作为接收机中的关键模块,其性能指标直接决定了本振信号的精度和纯度。由于整数分频锁相环的参考频率为接收机信道宽度,且锁相环的环路带宽要求小于其参考频率的十分之一。整数分频锁相环很难满足MICS接收机快速锁定,高分辨率的要求。因此,文中设计的频率合成器采用了小数分频锁相环结构。文中从基本的单元模块到系统架构,对小数分频锁相环进行了详细的理论分析。并在理论分析的基础上,设计了一个用于MICS无线收发系统的400MHz~430MHz的低功耗小数分频电荷泵锁相环。其中VCO采用四阶差分结构环形振荡器,divider采用六位脉冲吞咽可编程分频器,??调制器采用MASH1-1-1结构,电荷泵采用带镜像支路的电荷泵并用电压跟随器消除电荷共享,环路滤波器滤波器采用三阶RC无源滤波器以抑制调制器高频量化噪声。文中首先根据MICS接收机系统指标规划了小数分频锁相环各模块指标,并用MATLAB/Simulink建模验证了指标规划的合理性。其次,在Cadence Spectre平台下完成小数分频锁相环的设计仿真。再次,根据所设计的电路在Cadence Virtusoo下完成版图设计,所设计的锁相环芯片版图总面积为0.8mm*1.2mm(含PAD)。后仿真时,小数分频锁相环的工作电压为1.8V,输出频率范围:400MHz~430MHz,信道宽度为300kHz,锁定时间小于25us,小数杂散小于-50dBc,相位噪声为-104dBc/Hz@1MHz。设计的锁相环,满足MICS无线接收机的性能指标要求。该小数分频锁相环芯片在GSMC0.18um工艺下流片,采用QFN24管脚封装。测试时,VCO输出频率范围为95MHz~741.7MHz,相位噪声为-91.47dBc/Hz@1MHz。分频器能正常工作,但整个锁相环无法锁定。后面对这次设计作了详细的总结,并提出了相应的改进措施。
[Abstract]:With the rapid growth of wireless communication market, there is an urgent demand for high performance and low cost RF integrated circuits. At the same time, the rapid development of semiconductor industry also provides the possibility for all communication modules to be integrated on one chip. Among them, the most difficult to integrate is to provide the local oscillator signal phase-locked loop. Because the phase noise of phase-locked loop is difficult to meet the phase noise requirements of wireless communication system. Therefore, there are more and more studies on all kinds of phase-locked loops. From integer frequency division to decimal frequency division, from analog to digital, the performance of phase-locked loop (PLL) is improved and the cost is reduced. As the key module of the receiver, the performance index of the frequency synthesizer directly determines the accuracy and purity of the local oscillator signal. Because the reference frequency of the integer frequency division phase-locked loop is the channel width of the receiver, and the loop bandwidth of the phase-locked loop is less than 1/10 of its reference frequency. Integer frequency division phase-locked loop is difficult to meet the requirements of fast locking and high resolution of MICS receiver. Therefore, the frequency synthesizer designed in this paper adopts the decimal frequency division phase-locked loop structure. In this paper, from the basic unit module to the system architecture, the decimal frequency division phase-locked loop is analyzed in detail. On the basis of theoretical analysis, a phase-locked loop of low power decimal charge pump for MICS wireless transceiver system is designed. Among them, VCO uses four-order differential ring oscillator, divider uses six-bit pulse swallowing programmable frequency divider, and divider adopts six-bit pulse swallowing programmable divider. The modulator adopts MASH1-1-1 structure, the charge pump adopts charge pump with mirror branch and the voltage follower is used to eliminate charge sharing. The loop filter adopts third-order RC passive filter to suppress the high frequency quantitative noise of modulator. In this paper, each module index of decimal frequency division phase-locked loop is planned according to the MICS receiver system index, and the rationality of the index planning is verified by MATLAB/Simulink modeling. Secondly, the design and simulation of phase-locked loop with decimal frequency division is completed on Cadence Spectre platform. Thirdly, according to the designed circuit, the layout design is completed under Cadence Virtusoo, and the total area of phase-locked loop chip layout is 0.8mm*1.2mm (including PAD). After simulation, the operating voltage of the phase-locked loop is 1.8 V, the output frequency range is 400MHz 鈮，
本文编号：2481845
[Abstract]:With the rapid growth of wireless communication market, there is an urgent demand for high performance and low cost RF integrated circuits. At the same time, the rapid development of semiconductor industry also provides the possibility for all communication modules to be integrated on one chip. Among them, the most difficult to integrate is to provide the local oscillator signal phase-locked loop. Because the phase noise of phase-locked loop is difficult to meet the phase noise requirements of wireless communication system. Therefore, there are more and more studies on all kinds of phase-locked loops. From integer frequency division to decimal frequency division, from analog to digital, the performance of phase-locked loop (PLL) is improved and the cost is reduced. As the key module of the receiver, the performance index of the frequency synthesizer directly determines the accuracy and purity of the local oscillator signal. Because the reference frequency of the integer frequency division phase-locked loop is the channel width of the receiver, and the loop bandwidth of the phase-locked loop is less than 1/10 of its reference frequency. Integer frequency division phase-locked loop is difficult to meet the requirements of fast locking and high resolution of MICS receiver. Therefore, the frequency synthesizer designed in this paper adopts the decimal frequency division phase-locked loop structure. In this paper, from the basic unit module to the system architecture, the decimal frequency division phase-locked loop is analyzed in detail. On the basis of theoretical analysis, a phase-locked loop of low power decimal charge pump for MICS wireless transceiver system is designed. Among them, VCO uses four-order differential ring oscillator, divider uses six-bit pulse swallowing programmable frequency divider, and divider adopts six-bit pulse swallowing programmable divider. The modulator adopts MASH1-1-1 structure, the charge pump adopts charge pump with mirror branch and the voltage follower is used to eliminate charge sharing. The loop filter adopts third-order RC passive filter to suppress the high frequency quantitative noise of modulator. In this paper, each module index of decimal frequency division phase-locked loop is planned according to the MICS receiver system index, and the rationality of the index planning is verified by MATLAB/Simulink modeling. Secondly, the design and simulation of phase-locked loop with decimal frequency division is completed on Cadence Spectre platform. Thirdly, according to the designed circuit, the layout design is completed under Cadence Virtusoo, and the total area of phase-locked loop chip layout is 0.8mm*1.2mm (including PAD). After simulation, the operating voltage of the phase-locked loop is 1.8 V, the output frequency range is 400MHz 鈮，
本文编号：2481845
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