面向密码算法的大位宽比特置换操作高速实现方案

发布时间：2018-04-13 20:18

本文选题：比特置换 + N-N置换　；参考：《电子与信息学报》2017年09期

【摘要】：针对面向字级优化的通用处理器,在应对密码算法中大位宽比特置换操作时效率较低的问题,该文提出2N-2N和kN-kN(k2)的大位宽比特置换操作高速实现方案。并针对方案中涉及的比特提取和比特提取-移位两种操作,分别提出专用扩展指令BEX,BEX-ROT。在此基础上,对专用指令硬件架构的高效设计进行研究,提出一种基于Inverse Butterfly网络统一硬件架构-RERS(Reconfigurable Extract and Rotation Shifter)及相应可重构路由算法,以最大限度地共享硬件资源,减小电路面积。实验结果表明,所提方案能够将处理器架构执行大位宽比特置换操作的指令条数缩减约10倍,大幅提升其处理效率。同时,由专用指令所带来的硬件资源开销和延迟开销均较低,不会影响到原架构正常工作频率。
[Abstract]:In order to solve the problem of low efficiency of large bit wide bit permutation operation in cryptographic algorithms, this paper proposes a high speed implementation scheme of large bit wide bit permutation operation based on 2N-2N and kN-kNnnk2).Aiming at the two operations of bit extraction and bit extraction-shift, a special extended instruction BEXX BEX-ROT is proposed.On this basis, the efficient design of the special instruction hardware architecture is studied, and a unified hardware architecture based on Inverse Butterfly network is proposed, and the corresponding reconfigurable Extract and Rotation shift algorithm is proposed to maximize the sharing of hardware resources and reduce the circuit area.Experimental results show that the proposed scheme can reduce the number of instruction bars of the processor architecture to perform large bit wide bit substitution operation by about 10 times, and greatly improve its processing efficiency.At the same time, the hardware resource overhead and the delay overhead brought by the special instruction are lower, which will not affect the normal working frequency of the original architecture.
【作者单位】：解放军信息工程大学;复旦大学专用集成电路与系统国家重点实验室;
【基金】：国家自然科学基金(61404175)~~
【分类号】：TN918.1

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