HEVC帧内预测算法的优化及FPGA实现

发布时间：2018-04-19 12:03

本文选题：HEVC + 视频编码　；参考：《哈尔滨工业大学》2017年硕士论文

【摘要】：相比于H.264视频压缩标准,近期提出的新标准HEVC(High Efficiency Video Coding),在以增加计算复杂度为代价的前提下,压缩效率提高了近50%。与此同时,复杂的算法也需要更好的设计方法来迎接高视频分辨率带来的挑战。因此,对HEVC标准中的各部分功能的进一步优化具有非常重要的有意义。帧内预测作为HEVC的一个重要组成部分,通过利用位于当前编码单元的左方以及上方的相邻参考像素得到当前块的重建块的过程。帧内预测的复杂性主要体现在编码单元结构灵活性的增长和预测模式数量的增加。在参考模型HM中,采用了一种灵活的四叉树块划分结构对编码单元进行分割,根据不同区域纹理复杂度的不同,对于复杂度较高的预测单元采用较小的块进行预测编码,反之采用较大的块进行编码,在预测和转换编码过程中进一步提高效率,同时在进行模式选择时为所有预测单元定义了35种模式。本课题主要对HEVC帧内预测中编码单元的划分方式以及预测单元的模式选择两个方面展开研究。本文的主要研究内容包括HEVC帧内预测算法的HM实现和FPGA实现。本文利用Sobel算子对HEVC中编码单元进行划分以及对预测单元的模式选择进行判断,在HM中对算法进行验证。HM中的实现主要对编码时间、率失真性能等方面进行测试,并与HEVC标准进行比较,验证算法的优越性。帧内预测算法在FPGA上的实现用到了Xilinx Virtex6 ML605开发板,通过WinDriver驱动ML605板卡,在Win Driver生成的应用层程序的调控下,图像数据利用PCIE接口的DMA控制器从上位机传入FPGA,接下来对导入的图像数据进行帧内预测处理,最后将得到的预测图像数据通过DMA传送回上位机,并用MATLAB对图像数据进行译码后观察处理结果。帧内预测算法的FPGA实现包括数据的存储、图像划分、模式选择、参考像素的处理、变换、量化、反变化、反量化等模块的Verilog HDL实现。实验结果表明,相对HEVC标准,HEVC帧内预测算法进行优化后,在保证图像质量及压缩效率的同时,编码时间有了大幅度的减少,并且完成了HEVC帧内预测算法的FPGA实现对图像进行压缩处理。
[Abstract]:Compared with H.264 video compression standard, the recently proposed new standard HEVC(High Efficiency Video coding improves the compression efficiency by nearly 50% at the cost of increasing computational complexity.At the same time, complex algorithms also need better design methods to meet the challenges of high video resolution.Therefore, it is very important to optimize the function of each part of HEVC standard.Intra-frame prediction is an important part of HEVC. The reconstruction block of the current block is obtained by using adjacent reference pixels located on the left side of the current coding unit as well as adjacent reference pixels above the current coding unit.The complexity of intra prediction is mainly reflected in the increase of coding unit structure flexibility and the increase in the number of prediction modes.In the reference model HM, a flexible quadtree block partition structure is used to segment the coding unit. According to the different texture complexity of different regions, the prediction unit with high complexity is predicted by smaller blocks.On the contrary, large blocks are used for coding, which can further improve the efficiency in the prediction and conversion coding process. At the same time, 35 patterns are defined for all prediction units in the process of mode selection.In this paper, the division of coding units in HEVC intra prediction and the mode selection of prediction units are studied.The main contents of this paper include HM implementation and FPGA implementation of HEVC intra prediction algorithm.In this paper, the coding unit in HEVC is divided by Sobel operator and the mode selection of prediction unit is judged. The implementation of the algorithm in HM is mainly tested on coding time, rate-distortion performance and so on.Compared with HEVC standard, the superiority of the algorithm is verified.The implementation of intra prediction algorithm on FPGA uses the Xilinx Virtex6 ML605 development board, which drives the ML605 card through WinDriver, under the control of the application layer program generated by Win Driver.The image data is passed into FPGA by the DMA controller of PCIE interface, then the imported image data is processed by intra prediction. Finally, the predicted image data is transmitted back to the host computer through DMA.The image data is decoded by MATLAB and the results are observed and processed.The FPGA implementation of intra prediction algorithm includes data storage, image partition, mode selection, processing of reference pixels, transformation, quantization, inverse change, inverse quantization and Verilog HDL implementation.The experimental results show that compared with the HEVC standard, the coding time is greatly reduced while the image quality and compression efficiency are guaranteed.And the FPGA implementation of HEVC intra prediction algorithm is completed.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN919.81;TN791

【参考文献】