准循环LDPC码的设计与FPGA实现

发布时间：2018-05-29 05:06

本文选题：循环扩展 + 准循环编码　；参考：《哈尔滨工业大学》2017年硕士论文

【摘要】：LDPC的码型构造直接影响其在不同通信系统中的性能,本文在EG_LDPC码基础上,利用循环扩展的方式构造了(8176,6135)QC_LDPC码。此QC_LDPC码的校验矩阵密度为5111,有很大的稀疏性。且在SPA译码方式下,译码性能在信噪比为2.8d B时误码率急剧下降,具有良好的瀑布性,当信噪比为3.2d B时误码率已经达到了10-10,仍然没有误码平层的出现。(8176,6135)QC_LDPC码低复杂度,高信噪比下没有误码平层的优势,此特点符合光纤通信对信道编码的要求,将在光纤通信中有良好的应用前景,所以对QC_LDPC码进行了FPGA实现,以得到更好的实际应用效果。根据(8176,6135)的QC_LDPC由单位置换子矩阵构成的特点,选择准循环的编码算法,构造出了具有准循环形式的生成矩阵。利用生成矩阵准循环的特点在FPGA中设计使用寄存器的硬件编码器。QC_LDPC码的译码方面,选择了误码性能最好的SPA算法作为性能仿真的算法。但是为了减少硬件的浮点运算,在QC_LDPC码的译码器实现方案中采用了SPA的简化算法min_sum。在整个译码器设计方案中,主要采用了串并结合的译码方法,根据QC_LDPC的特点,将各个循环子矩阵进行并行运算,子矩阵的内部进行串行运算,尽可能的减少迭代译码时间。并提出了将节点判断模块与校验节点和变量节点模块相结合的方式,进一步减少迭代译码的时间。最后将编码器与译码器在Xilinx的Virtex5芯片进行实现。在50MHz的时钟频率下,编码器可以实现连续的串行输出,达到67Mbps的吞吐率,译码器可以实现多帧并行处理,每帧的吞吐率为39Mbps,在硬件资源允许的条件下,则可以达到更高的吞吐率。
[Abstract]:The construction of LDPC code directly affects its performance in different communication systems. Based on EG_LDPC code, this paper constructs a QC LDPC-code based on cyclic expansion. The check matrix density of this QC_LDPC code is 5111, which is very sparse. In the SPA decoding mode, the BER decreases sharply when the SNR is 2.8 dB, and has good waterfall. When SNR is 3.2 dB, the BER has reached 10-10, and there is still no BER level layer. There is no BER flat layer in high SNR, which meets the requirement of channel coding in optical fiber communication. It will have a good application prospect in optical fiber communication, so the QC_LDPC code is implemented by FPGA to get better practical application effect. According to the characteristic that the QC_LDPC of Y8176 / 6135) is composed of unit permutation submatrix, the quasi-cyclic coding algorithm is selected and the generating matrix with quasi-cyclic form is constructed. Based on the characteristic of quasi-cycle of generating matrix, the decoding of the hardware encoder. QCLDPC using register is designed in FPGA. The SPA algorithm with the best performance of error code is chosen as the algorithm of performance simulation. But in order to reduce the floating-point operation of the hardware, the SPA simplified algorithm minsumsum is used in the implementation of the decoder of QC_LDPC code. In the design of the decoder, the serial parallel decoding method is mainly used. According to the characteristics of QC_LDPC, each cyclic submatrix is run in parallel, and the submatrix is operated serially, so as to reduce the iterative decoding time as much as possible. The method of combining node judgment module with check node and variable node module is proposed to further reduce the time of iterative decoding. Finally, the encoder and decoder are implemented in Xilinx Virtex5 chip. At the clock frequency of 50MHz, the encoder can realize serial output continuously and achieve the throughput of 67Mbps. The decoder can realize multi-frame parallel processing. The throughput rate of each frame is 39Mbps. A higher throughput rate can be achieved.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22;TN791

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