基于数字锁相环的星载光谱仪本地时钟源设计

发布时间：2018-05-29 07:33

本文选题：数字锁相环 + 反馈控制　；参考：《电子与信息学报》2017年10期

【摘要】：该文针对太阳同步轨道卫星由于通讯误码导致卫星时钟不正常翻转造成的错误,提出了纠错策略。基于卫星时钟和本地时钟授时误差互补的特点,设计了一种应用于低频输入信号和大倍频系数条件下的数字锁相环(DPLL),利用数字锁相环使本地时钟跟踪卫星时钟秒脉冲的相位波动,实时消除本地时钟的累积误差。对该时钟源进行了理论分析和实验验证,用现场可编程门阵列(FPGA)予以实现。实验表明,该设计实现的时钟源可以实时纠正卫星时钟出现的秒脉冲不正常翻转、秒脉冲丢失、时间包跳变、时间包丢失等错误,最短可以在5个输入时钟周期内进入锁定状态,稳定工作时每秒累积误差小于100μs,可作为星载光谱仪本地时钟源使用。
[Abstract]:In this paper, an error correction strategy is proposed to solve the error caused by the abnormal turning of the satellite clock caused by the communication error code of the sun-synchronous orbit satellite. Based on the complementary error between satellite clock and local clock, A digital phase-locked loop (DPLL) applied to low frequency input signal and large frequency doubling coefficient is designed. The local clock can track the phase fluctuation of the satellite clock second pulse and eliminate the cumulative error of the local clock in real time by using the digital phase-locked loop (DPLL). The theoretical analysis and experimental verification of the clock source are carried out and implemented with FPGA (Field Programmable Gate Array). The experiments show that the designed clock source can correct the errors such as abnormal rotation of second pulse, loss of second pulse, jump of time packet, loss of time packet, etc. The shortest time can be locked in 5 input clock cycles, and the cumulative error per second is less than 100 渭 s, which can be used as the local clock source of spaceborne spectrometer.
【作者单位】：中国科学技术大学环境科学与光电技术学院;中国科学院安徽光学精密机械研究所环境光学与技术重点实验室;上海卫星工程研究所;
【基金】：国家自然科学基金(41275037) 安徽省杰出青年科学基金(1308085JGD03)~~
【分类号】：TN911.8;V443

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