面向5G的SCMA技术研究与实现

发布时间：2018-06-15 11:27

本文选题：非正交多址 + 稀疏码分多址　；参考：《电子科技大学》2017年硕士论文

【摘要】：移动互联网和物联网是未来5G的重要应用场景。高速发展的移动互联网和物联网要求移动通信网络能够提供海量接入服务。多址接入技术是移动通信的一种重要空口技术,它能够有效的提高移动网络用户接入数。因此,研究和设计新的多址技术具有重大的研究价值和现实意义。稀疏码分多址(SCMA)是一种新型的非正交多址技术,它能够较好的适应5G应用场景,因此广泛的受到业界和学术界的关注。在5G标准尚未制定完成之前,本文以SCMA为立足点对5G的多址技术做出探索性研究,目的在于设计出适合5G的多址技术方案。本文主要从码本设计准则和低复杂度译码两个方面对SCMA这种非正交多址技术展开研究。首先,本文重点分析了基于星座实部和虚部混排这种经典的码本设计准则。然后按照码本优化设计的基本思路,提出了一种分配星座能量和旋转相位的码本设计准则。仿真结果表明基于新的码本设计准则设计的码本性能存在较大的优势。鉴于目前码本设计尚无统一的准则,因此基于分配星座能量和旋转相位的码本设计准则是一种不错的码本设计备选方案。然后,本文在研究了基于因子分解图的迭代MPA译码算法基础上提出了一种对数域基于因子分解子图的迭代MPA译码算法。一方面,一种特殊结构的因子分解子图在基本MPA的基础上替代普通的因子分解图,降低了消息迭代运算过程中功能节点更新消息的有效运算。另一方面,雅可比对数近似运算被引入消息传递算法,简化了消息传递算法中的复杂运算。分析和仿真表明改进的译码算法以小幅度的性能损失能够换取译码计算复杂度的大幅度降低。因此,改进的译码算法能够在计算复杂度和误码性能之间取得不错的折中。最后,本文根据改进的译码算法提出了一种基于FPGA的SCMA译码器实现方案,并且利用Verilog语言设计了6个用户的SCMA译码器。电路综合结果表明设计的SCMA译码器占用芯片约17%的资源。测试结果表明SCMA译码器完成一次多用户联合迭代译码消耗约246个时钟周期。同时,测试误码率和Matlab仿真误码率曲线基本一致,基本满足设计要求。
[Abstract]:Mobile Internet and Internet of things are the important application scenarios of 5 G in the future. The rapid development of mobile Internet and Internet of things requires mobile communication network to provide mass access services. Multiple access (mai) is an important empty port technology in mobile communication. It can effectively improve the number of mobile network users. Therefore, the research and design of new multiple-access technology has great research value and practical significance. Sparse Code Division multiple access (SCMA) is a new non-orthogonal multiple access technology, which can adapt to 5G applications, so it has been widely concerned by the industry and academia. Before the 5G standard has been formulated, this paper takes SCMA as the foothold to do exploratory research on 5G multiple access technology, with the aim of designing a scheme suitable for 5G multiple access technology. In this paper, the non-orthogonal multiple access (NOAA) technique of SCMA is studied from two aspects: codebook design criterion and low complexity decoding. Firstly, the classical codebook design criterion based on constellation real part and virtual part is analyzed. Then, according to the basic idea of codebook optimization design, a codebook design criterion for allocating constellation energy and rotation phase is proposed. The simulation results show that the code nature based on the new codebook design criterion has great advantages. Since there is no uniform criterion for codebook design at present, the codebook design criterion based on the allocation of constellation energy and rotation phase is a good codebook design alternative. Then, an iterative MPA decoding algorithm in logarithmic domain based on factorization subgraph is proposed based on the study of iterative MPA decoding algorithm based on factorization graph. On the one hand, a special structure factorization subgraph replaces the common factorization graph on the basis of basic MPA, which reduces the effective operation of updating message in the process of message iteration. On the other hand, Jacobian logarithmic approximation is introduced into message passing algorithm, which simplifies the complex operation in message passing algorithm. The analysis and simulation show that the improved decoding algorithm can reduce the computational complexity of decoding by a small margin. Therefore, the improved decoding algorithm can achieve a good compromise between computational complexity and error performance. Finally, according to the improved decoding algorithm, this paper proposes a FPGA based SCMA decoder implementation scheme, and uses Verilog language to design six users of SCMA decoder. The circuit synthesis results show that the designed SCMA decoder occupies about 17% of the chip resources. The test results show that it takes about 246 clock cycles for the SCMA decoder to complete a multiuser joint iterative decoding. At the same time, the test BER curve is basically the same as Matlab simulation BER curve, which basically meets the design requirements.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN929.5

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